AN 987: Fa'afouga Fa'atete'e Vaega
Toe fetuutuunai A'oa'oga

Fa'afou Fa'afou Fa'atonu Fa'atonu Fa'atonu mo le Intel® ™ Agilex F-Series FPGA Development Board

O lenei tusi talosaga o lo'o fa'aalia ai le fa'afouga fa'afou fa'aputuga (SUPR) i luga ole Intel ® F-Series FPGA Development Board. O le vaega toe fetuutuunai (PR) e mafai ai ona e toe fetuutuunai se vaega o le Intel FPGA ma le malosi, ae o loʻo faʻaauau pea le faʻaogaina o le FPGA o totoe. E fa'atino e le PR le tele o tagata i totonu o se itulagi fa'apitoa i lau mamanu, e aunoa ma le a'afiaina o galuega i vaega i fafo atu o lenei itulagi. O lenei metotia e maua ai le advan neitagi faiga e tele galuega fa'atino-fa'asoa fa'atasi FPGA punaoa:

• Fa'ataga le toe fa'atulagaina o taimi ta'avale
• Faʻateleina le faʻalauteleina o mamanu
• Fa'aitiitia le taimi fa'aletonu faiga
• Lagolagoina galuega fa'aopoopo taimi-multiplexing i le mamanu
• Faʻaititia le tau ma le faʻaaogaina o le eletise e ala i le faʻaogaina lelei o avanoa laupapa

O le a le Static Update Partial Reconfiguration?

I le PR masani, soʻo se suiga i le itulagi faʻamautu e manaʻomia ai le toe tuʻufaʻatasia o tagata taʻitasi. Ae ui i lea, faʻatasi ai ma le SUPR e mafai ona e faʻamalamalamaina se itulagi faʻapitoa e mafai ai ona suia, e aunoa ma le manaʻomia o le toe tuʻufaʻatasia o tagata. O lenei metotia e aoga mo se vaega o se mamanu atonu e te manaʻo e sui mo le faʻaitiitia o lamatiaga, ae e le manaʻomia ai le toe faʻatulagaina o taimi.

1.1. Fa'atonuga Manaoga
O lenei aʻoaʻoga e manaʻomia mea nei:

• Fa'amasani fa'avae ile Intel Quartus® Prime Pro Edition FPGA fa'atinoina le fa'atinoga ma le poloketi files.
•  Fa'apipi'iina o le Intel Quartus Prime Pro Edition version 22.3, fa'atasi ai ma le Intel Agilex masini lagolago.
• Mo le faʻatinoga o le FPGA, o le JTAG feso'ota'iga ma le Intel Agilex F-Series FPGA development board i luga o le nofoa.
• La'u mai le Fa'ailoga Fa'asinomaga Files. Fa'amatalaga Fa'atatau
• Ta'iala mo Tagata Fa'aoga Fa'atonu Fa'apitoa
• Fa'aa'oa'oga Fa'atonu Fa'apitoa
• Fa'aa'oa'oga i luga ole laiga ole Fa'atonuga Fa'apitoa

Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'ailoga a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua. *O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.
ISO 9001:2015 Resitala
1.2. Fa'asinoga Design Overview
O lenei mamanu faʻasino e aofia ai le tasi, 32-bit counter. I le tulaga o le laupapa, o le mamanu e faʻafesoʻotaʻi le uati i se puna 50MHz, ona faʻafesoʻotaʻi lea o le gaioiga i le fa LED i luga o le laupapa. O le filifilia o mea e maua mai le fata fa'atau, i se fa'asologa fa'apitoa, e mafua ai ona emoemo LED i se taimi fa'apitoa. O le pito i luga_counter module o le SUPR region.
Ata 1. Fuafuaga Fa'asinomaga Mafolafola

1.3. Fa'afou Fa'afou Itulagi I lugaview
O le ata o loʻo i lalo o loʻo faʻaalia ai le poloka poloka mo se PR design e aofia ai se itulagi SUPR. O le poloka A o le pito pito i luga ole itulagi. Block B o le itulagi SUPR. Block C o le PR vaeluaga.
Ata 2. PR Design ma SUPR Region

• A Top Static Region-o loʻo iai le faʻataʻitaʻiga e le suia. O le suia o lenei itulagi e mana'omia ai le toe tu'ufa'atasia o tagata uma e feso'ota'i. O le vaega fa'amautu e aofia ai le vaega o le mamanu e le suia mo so'o se tagata. O lenei itulagi e mafai ona aofia ai puna'oa pito i tua ma autu o masini. E tatau ona e resitalaina uma fesoʻotaʻiga i le va o le SUPR ma le PR vaeluaga i le itulagi faʻamau. O lenei mana'oga e fesoasoani e fa'amautinoa le tapunia o le taimi mo so'o se tagata, e fa'atatau i le itulagi tu'usa'o.
• B SUPR Itulagi—o lo'o i ai na'o manatu autu e ono suia mo le fa'aitiitia o tulaga lamatia, ae e le mana'omia ai le toe fa'atulagaina o taimi. O le itulagi SUPR e tutusa manaʻoga ma tapulaʻa e pei o le PR vaeluaga. O le vaeluaga o le SUPR e mafai ona aofia ai na'o punaoa autu. O le mea lea, o le vaeluaga o le SUPR e tatau ona avea ma se vaeluaga a tamaiti o le vaega pito i luga o le a'a o lo'o i ai le pito o le mamanu ma uati. Suia le itulagi SUPR e maua ai se SRAM Object File (.sof) e fetaui ma Raw Binary uma ua tuufaatasia File (.rbf) filemo PR vaeluaga C.
• C PR Vaeluaga-o loʻo i ai le faʻatonuga faʻapitoa e mafai ona e toe faʻapipiʻiina i le taimi o le taʻavale ma soʻo se mamanu mamanu e fetaui ma ausia le tapuni taimi i le taimi o le tuʻufaʻatasia.

1.4. La'u mai le Fa'ailoga Fa'asinomaga Files
O lo'o avanoa le a'oa'oga toe fa'atulagaina vaega i le nofoaga nei: https://github.com/intel/fpga-partial-reconfig
Ina ia sii maia le aoaoga:

1. Kiliki Clone pe download.
2. Kiliki i lalo le ZIP. Tatala le fpga-partial-reconfig-master.zip file.
3. Su'e i le a'oa'oga/agilex_pcie_devkit_blinking_led_supr subfolder e maua ai le mamanu fa'asino.
   O le pusa mafolafola e aofia ai mea nei files:
   Laulau 1. Fa'ailoga Fa'asinomaga Files

File Igoa	Fa'amatalaga
pito i luga. sv	Tulaga maualuga file o loʻo i ai le faʻatinoga mafolafola o le mamanu. O lenei module e fa'atino vave le blinking_led sub-partition ma le top_counter module.
t op_counter . sv	Fa'atauga 32-bit pito i luga e pulea sa'o le LED [1]. O galuega fa'amau a le fata e pulea ai le LED [0], fa'apea fo'i le malosi o le LED [2] ma le LED [3] e ala i le module blinking_led.
emoemo_ta'ita'ia. sdc	Fa'amatala fa'agata taimi mo le poloketi.
emoemo_ta'ita'ia. sv	I lenei aʻoaʻoga, e te faʻaliliuina lenei module i se vaeluaga PR matua. E maua e le module le gaioiga resitalaina o le top_counter module, lea e pulea le LED [2] ma le LED [3].
blinking_led.qpf	Poloketi Intel Quartus Prime file o lo'o i ai le lisi o toe iloiloga uma i totonu o le poloketi.
emoemo_ta'ita'i . qs f	Fa'atonu Intel Quartus Prime file o lo'o i ai tofitofiga ma fa'atulagaga mo le poloketi.

Fa'aaliga: O le supr folder o loʻo i ai le seti atoa o filee te fatuina e faʻaaoga ai lenei talosaga fa'amatalaga. Fa'asino i mea nei files i soo se taimi a o faagasolo le savali.
1.5. Fa'asinomaga Design Walkthrough
O laasaga nei o loʻo faʻamatalaina ai le faʻatinoina o le SUPR ma se mamanu mafolafola:

• Laasaga 1: Amataina
• Laasaga 2: Fausia Design Partitions
• Laasaga 3: Fa'asoa Fa'atonuga ma Fa'atonu Itulagi
• Laasaga 4: Fa'amatala Tagata
• Laasaga 5: Fausia Faʻamatalaga
• Laasaga 6: Tuufaatasia le Toefuataiga Faavae
• Laasaga 7: Seti le PR Fa'atinoga Toe Iloiloga
• Laasaga 8: Suia le SUPR Logic
• Laasaga 9: Polokalama le Komiti Faatino

Ata 3. SUPR Compilation Flow

1.5.1. Laasaga 1: Amataina
Ina ia kopi le mamanu faasinomaga files i lou siosiomaga faigaluega ma tuufaatasia le blinking_led mafolafola mamanu:

1. Ae e te le'i amataina, la'u mai le Reference Design Files i le itulau e 5.
2. Fausia le agilex_pcie_devkit_blinking_led_supr directory i lau siosiomaga faigaluega.
3. Kopi le la'u mai a'oa'oga/agilex_pcie_devkit_blinking_led/flat sub-folder i le agilex_pcie_devkit_blinking_led_supr directory.
4. I le polokalama Intel Quartus Prime Pro Edition, kiliki File ➤ Tatala Poloketi ma tatala /flat/blinking_led.qpf.
5. Ina ia tuufaatasia le mamanu faavae, kiliki Processing ➤ Start Compilation. Ole lipoti ole Timing Analyzer e tatala otometi pe a mae'a le tu'ufa'atasiga. E mafai ona e tapuni le Timing Analyzer mo le taimi nei.

1.5.2. Laasaga 2: Fausia Design Partitions
Fausia ni vaeluaga o mamanu mo itulagi ta'itasi e te mana'o e toe fetuutuuna'i se vaega. E mafai ona e fatuina soʻo se numera o vaeluaga tutoʻatasi poʻo PR itulagi i lau poloketi. Mulimuli i laasaga nei e fai ai ni vaeluaga mo le u_blinking_led instance e pei o le PR partition, ma le u_top_counter instance o le SUPR region:

1. Kiliki taumatau o le u_blinking_led instance i le Project Navigator ma kiliki Design Partition
   ➤ Toe fetuutuunai. O se ata vaeluaga mamanu e aliali i tafatafa o fa'ata'ita'iga ta'itasi o lo'o fa'atulagaina o se vaeluaga.
   Ata 4. Fausia Fuafuaga Vaevaega
2. Toe fai le la'asaga 1 e fai ai se vaeluaga mo le fa'ata'ita'iga u_top_counter.
3. Kiliki Assignments ➤ Design Partitions Window. O le faamalama o loʻo faʻaalia uma vaega mamanu i totonu o le poloketi.
   Ata 5. Fa'amalama Vaevaega Fua
   
4. Kiliki faalua le blinking_led Partition Name cell e toe faaigoa i le pr_partition. Fa'apena fo'i, toe fa'aigoa le top_counter partition i le supr_partition.
   I le isi itu, o le fa'aopoopoina o laina nei i le blinking_led.qsf e fausia ai vaega nei:
   set_instance_assignment -igoa PARTITION pr_partition \ -to u_blinking_led -entity pito i luga
   set_instance_assignment -igoa PARTIAL_RECONFIGURATION_PARTITION ON \ -to u_blinking_led -entity pito i luga
   seti_instance_assignment -igoa PARTITION supr_partition \ -to u_top_counter -entity pito i luga
   set_instance_assignment -igoa PARTIAL_RECONFIGURATION_PARTITION ON \ -to u_top_counter -entity pito i luga

1.5.3. Laasaga 3: Fa'asoa Fa'atonuga ma Fa'atonu Itulagi
Mo su'esu'ega fa'avae uma e te faia, e fa'aogaina e le Compiler le vaega fa'asoasoaina o le PR vaeluaga e tu'u ai le tagata e fetaui i totonu o le itulagi fa'apolopolo. Mulimuli i laasaga nei e suʻe ma tofia se PR itulagi i le masini fola fuafuaga mo lau toe iloiloga faavae:

1. I le Project Navigator Hierarchy tab, kiliki-matau le u_blinking_led instance, ona kiliki lea Logic Lock Region ➤ Create New Logic Lock Region. E aliali mai le itulagi i le fa'amalama Logic Lock Regions.
2. Fa'ailoa se vaega ole lautele ole 5 ma le maualuga ole 5.
3. Fa'ailoa le fa'atūlaga fa'atūlaga fa'amaopoopo mo u_blinking_led i le Origin column. O le amataga e fetaui ma le pito i lalo agavale o le itulagi. Fa'ailoa le Amataga o le X166_Y199. E fuafua e le Compiler (X170 Y203) o le fa'amaopoopo pito i luga taumatau.
4. Fa'aagaaga le Fa'aagaga ma le Autu-Na'o filifiliga mo le itulagi.
5. Kiliki faalua le filifiliga Itulagi Routing. O lo'o fa'aali mai le pusa fa'atalanoaga o Fa'asinomaga Loka Loka Fa'aitulagi.
6. Mo le Ituaiga Auala, filifili Fixed with expansion. O lenei filifiliga e otometi lava ona tu'uina atu le umi Fa'alautele o le tasi.
7. Toe fai laasaga muamua e vaevae ai punaoa nei mo le u_top_counter partition:
   • Maualuluga—5
   • Lautele—5
   • Amataga—X173_Y199
   • Itulagi Fa'ata'ita'i- Fa'amauina ma fa'alautele ma Fa'alautele le umi o le tasi.
   • Faasao—I luga
   • Na'o Autu—I luga
   Ata 6. Fa'amalama Fa'aitulagi Loka Logic
   Fa'aaliga: E tatau ona lapo'a atu le itulagi o auala nai lo le vaega o lo'o tu'u ai, ina ia maua ai le fa'aopoopo atili fetu'una'i mo le ta'avale a le Compiler.tagu, pe a taʻitaʻia e le Compiler tagata eseese.
8. E tatau ona fa'apipi'i i lau fa'atūlaga le fa'amana'oga blinking_led. Ina ia filifili le itulagi e tu'u i ai e ala i le su'eina o le node i Chip Planner, kiliki-matau le u_blinking_led region name i le Logic Lock Regions window, ona kiliki lea Su'e Node ➤ Su'e ile Chip Planner.
9.  I lalo o Lipoti Vaega, kiliki-lua Lipoti Design Vaega. O le Chip Planner e fa'ailoa ma fa'ailoga lanu le itulagi.

Ata 7. Node Fuafuaga Chip Nofoaga mo blinking_led
I le isi itu, o le fa'aopoopoina o laina nei i le blinking_led.qsf e fausia ai vaega nei:
set_instance_assignment -igoa PARTITION pr_partition -to \ u_blinking_led -entity pito i luga
set_instance_assignment -igoa PARTIAL_RECONFIGURATION_PARTITION ON \ -to u_blinking_led -entity pito i luga
seti_instance_assignment -igoa PARTITION supr_partition -i le u_top_counter \ -entity pito i luga
set_instance_assignment -igoa PARTIAL_RECONFIGURATION_PARTITION ON -to \ u_top_counter -entity pito i luga
seti_instance_assignment -igoa PLACE_REGION "X166 Y199 X170 Y203" -to \ u_blinking_led
set_instance_assignment -igoa RESERVE_PLACE_REGION ON -e u_blinking_led
set_instance_assignment -igoa CORE_ONLY_PLACE_REGION ON -e u_blinking_led
seti_instance_assignment -igoa REGION_NAME pr_partition -i u_blinking_led
seti_instance_assignment -igoa ROUTE_REGION "X165 Y198 X171 Y204" -to \ u_blinking_led
set_instance_assignment -igoa RESERVE_ROUTE_REGION OFF -e u_blinking_led
seti_instance_assignment -igoa PLACE_REGION "X173 Y199 X177 Y203" -i \ u_top_counter
set_instance_assignment -igoa RESERVE_PLACE_REGION ON -to u_top_counter
set_instance_assignment -igoa CORE_ONLY_PLACE_REGION ON -to u_top_counter
seti_instance_assignment -igoa REGION_NAME supr_partition -i le u_top_counter
seti_instance_assignment -igoa ROUTE_REGION "X172 Y198 X178 Y204" -i \ u_top_counter
set_instance_assignment -igoa RESERVE_ROUTE_REGION OFF -i le u_top_counter
1.5.4. Laasaga 4: Fa'amatala Tagata

O lenei mamanu fa'asinomaga e fa'amatalaina ai ni tagata eseese se tolu mo le vaega PR e tasi, ma le tasi tagata SUPR mo le itulagi SUPR. Mulimuli i laasaga nei e faʻamalamalama ma aofia ai nei tagata i lau poloketi. Afai e fa'aaoga le Intel Quartus Prime Text Editor, tape le Add file
i le galuega o lo'o iai nei pe a fa'asaoina le files.

1. Fausia fou blinking_led_slow.sv, blinking_led_empty.sv, ma top_counter_fast.sv SystemVerilog files i lau tusi galuega. Fa'amaonia o le blinking_led.sv o lo'o i ai i le lisi galue.
2.  Ulufale mea nei mo le SystemVerilog files:
   Laulau 2. Fa'asinomaga Design Personas SystemVerilog
   

   File Igoa	Fa'amatalaga	Code
   blinking_led_slow. sv	Emo fa'agesegese ia LED	taimi 1 ps / 1 ps 'default_nettype leai se module blinking_led_slow // uati uati uaea ulufale, toe seti uaea ulufale, uaea ulufale [31:01 counter, // Fa'ailo fa'atonutonu mo le uaea fa'aola le LED led_two_on, uaea gaosi led_three_on localparam COUNTER_TAP = 27; reg led_two_on_r; vae ta'ita'i tolu; assign led_two_on = led_two_on_r; assign led_three_on = led_three_on_r; always_ff @(posedge uati) amata led_two_on_r <= counter[COUNTER_TAP]; led_three_on_r <= counter[COUNTER_TAP]; endmodule pito
   emoemo_le_fua. sv	E tumau pea LED	timescale 1 ps / 1 ps 'default_nettype none module blinking_led_empty( // uati ulufale uaea uati, toe setiina uaea ulufale, uaea ulufale [31:01 counter, // faailoilo pulea mo le LEC- uaea output led_two_on, uaea output led_three_on
   faaauau…

   File Igoa	Fa'amatalaga	Code
   		// O lo'o fa'agaoioi le ta'ita'i maualalo assign led_two_on = l'IDO; tofi led_three_on = 11b0; endmodule
   top_counter_fast.sv	Lua SUPR	'taimi 1 ps / 1 ps
   	tagata	Thdefault_nettype leai se module top_counter_fast
   		// Fa'ailo fa'atonutonu mo le uaea fa'apipi'i LED led_one_on, uaea fa'aola [31:0] faitau, // uati fa'aoga uati.
   		); localparam TAP TAP = 23; reg [31:0] faitau_d; tofi numera = count_d; assign led_one_on = ount_d[COUNTER_TAP]; always_ff @(posedge clock) amata faitau_d <= faitau_d + 2; i'uga
   		.:module

3.  Kiliki File ➤ Save As ma sefe le .sv files i le lisi o galuega o lo'o iai nei.

1.5.5. Laasaga 5: Fausia Faʻamatalaga
O le PR design flow e fa'aogaina ai le toe teuteuga o galuega i le polokalama Intel Quartus Prime. O lau mamanu muamua o le toe teuteuga faavae, lea e te faʻamalamalamaina ai tuaoi o le itulagi faʻamautu ma reconfigurable itulagi i luga o le FPGA. Mai le toe iloiloga faavae, e te faia ni toe teuteuga faaopoopo. O nei toe iloiloga o loʻo i ai faʻatinoga eseese mo itulagi PR. Ae ui i lea, o faʻataʻitaʻiga uma o le faʻatinoga o le PR e faʻaogaina le tuʻufaʻatasia pito i luga ma le faʻasologa o taunuuga mai le toe iloiloga faavae. Ina ia tu'ufa'atasia se PR design, e te faia se iloiloga fa'atinoina o le PR mo tagata ta'itasi. E le gata i lea, e tatau ona e tuʻuina atu le Vaega Toefaʻatulagaina - Faʻavae poʻo le Faʻasalaga Faʻapitoa - Faʻatonuga Faʻatinoina o le ituaiga mo toe teuteuga taʻitasi. O le laulau o lo'o i lalo o lo'o lisiina ai le igoa toe teuteu ma le ituaiga toe teuteuga mo toe teuteuga taitasi. O le toe iloiloga impl_blinking_led_supr_new.qsf o le faatinoga o le tagata SUPR.
Laulau 3. Su'ega Igoa ma Ituaiga

Suafa Igoa	Ituaiga Toe Iloilo
fa'ata'imata	Toe fetuutuunai vaega - Fa'avae
blinking_led_default	Vaega Toefa'atonu - Fa'atinoina o Tagata
blinking_led_slow	Vaega Toefa'atonu - Fa'atinoina o Tagata
blinking_led_empty	Vaega Toefa'atonu - Fa'atinoina o Tagata
impl_blinking_led_supr_new	Vaega Toefa'atonu - Fa'atinoina o Tagata

1.5.5.1. Fa'atulagaina o le Toefuata'iga Fa'avae
Mulimuli i laasaga nei e seti ai le blinking_led e fai ma toe teuteuga:

1. Kiliki Poloketi ➤ Toe Iloiloga.
2. Mo Ituaiga Toe Fuata'iga, filifili Vaega Toefa'atonu - Fa'avae.

Ole la'asaga lea e fa'aopoopoina mea nei ile blinking_led.qsf:
##blinking_led.qsf set_global_assignment -igoa REVISION_TYPE PR_BASE
1.5.5.2. Fausiaina o Faiga Fa'atino
Mulimuli i laasaga nei e fai ai le faʻatinoga o toe iloiloga:

1. I le pusa fa'atalanoaga o Fa'amatalaga, kiliki fa'alua < >.
2. I le igoa Toe Iloiloga, fa'asino le blinking_led_default ma filifili le blinking_led mo Fa'avae i le toe iloiloga.
3. Mo le ituaiga Toefuataiga, filifili Vaega Toefa'atonu - Fa'atinoga o Tagata.
4. Fa'agata le Seti o le toe teuteuga o lo'o iai nei.
5. Toe fai laasaga 2 e oo i le 5 e seti ai le ituaiga Toe Iloiloga mo isi toe iloiloga o le faatinoga:

Suafa Igoa	Ituaiga Toe Iloilo	Faʻavae i luga o le Revision
blinking_led_slow	Vaega Toefa'atonu - Fa'atinoina o Tagata	fa'ata'imata
blinking_led_empty	Vaega Toefa'atonu - Fa'atinoina o Tagata	fa'ata'imata
impl_blinking_led_supr_new	Vaega Toefa'atonu - Fa'atinoina o Tagata	fa'ata'imata

Ata 8. Fausiaina o Fa'atonuga Fa'atino

Ta'itasi .qsf file ua i ai nei le tofiga nei:
seti_global_assignment -igoa REVISION_TYPE PR_IMPL
seti_fa'atonu_totogi -igoa ENTITY_REBINDING nofoaga_tagata -i le u_top_counter
set_instance_assignment -igoa ENTITY_REBINDING nofoaga_tagata -i u_blinking_led
1.5.6. Laasaga 6: Tuufaatasia le Toefuataiga Faavae
Mulimuli i laasaga nei e tuʻufaʻatasia ai le toe iloiloga autu ma auina atu i fafo le faʻamautu ma le SUPR itulagi mo le faʻaaogaina mulimuli i toe iloiloga o faʻatinoga mo tagata fou PR:

1. Seti le blinking_led e pei o le Toe Iloiloga i le taimi nei pe afai e leʻi setiina.
2. I totonu o le Design Partitions Window, kiliki le (...) i tafatafa o le koluma pito i luga taumatau ma mafai ai le Post Final Export File koluma. E mafai foi ona e tape pe suia le faasologa o koluma.
3. Ina ia otometi le auina atu i fafo o le ata mulimuli o vaega o le mamanu o le PR faatino pe a uma ona tuufaatasia, faʻamaonia mea nei mo le Post Final Export File filifiliga mo vaega a'a ma SUPR. O le .qdb files auina atu i le lisi o galuega faatino e ala i le faaletonu.
   • vaega_a'a—blinking_led_static.qdb
   • supr_partition—e emo_lea_supr_partition_final.qdb
   Ata 9. Ta'avale Lafoa'i i Fa'amalama Vaevaega Fa'ataI le isi itu, o tofitofiga .qsf o lo'o ta'ua i lalo e otometi lava ona fa'aulufale atu vaega pe a uma ona tu'ufa'atasia:
   seti_instance_assignment -igoa EXPORT_PARTITION_SNAPSHOT_FINAL \ blinking_led_static.qdb -to | -pito i luga
   set_instance_assignment -igoa EXPORT_PARTITION_SNAPSHOT_FINAL \ emo_led_supr_partition_final.qdb -i le u_top_counter \ -entity pito i luga
4. Ina ia tuufaatasia le toe teuteuga faavae blinking_led, kiliki Fa'agaioiga ➤ Amata
   Tuufaatasiga. I le isi itu, e mafai ona e faʻaogaina le poloaiga lenei e faʻapipiʻi ai lenei toe iloiloga:
   quartus_sh –flow compile blinking_led -c blinking_led A maeʻa le faʻapipiʻiina manuia, o mea nei files fa'aalia i le lisi o galuega:
   • blinking_led.sof
   • blinking_led.pr_partition.rbf
   • blinking_led.supr_partition.rbf
   • blinking_led_static.qdb
   • emo_led_supr_partition_final.qdb

1.5.7. Laasaga 7: Seti Fa'atonuga Fa'atinoga o le PR
E tatau ona e saunia le PR fa'atinoina toe iloiloga ae e te le'i fa'atupuina le PR bitstream mo masini polokalame. O lenei seti e aofia ai le faʻaopoopoina o le static region .qdb file e fai ma puna file mo toe iloiloga o faatinoga taitasi. E le gata i lea, e tatau ona e faʻamaonia
le vaega tutusa o le PR region. Mulimuli i laasaga nei e faʻatulaga ai le faʻatinoga o le PR:

1.  Ina ia seti le toe iloiloga o loʻo i ai nei, kiliki Project ➤ Revisions, filifili blinking_led_default o le Revision name, ona kiliki lea Set Current. I le isi itu, e mafai ona e filifilia le toe iloiloga o loʻo i ai nei i luga ole Intel Quartus Prime toolbar.
2. Ina ia faʻamaonia le puna saʻo mo lenei toe iloiloga o le faʻatinoga, kiliki Project ➤ Add/Remove Files i Poloketi. Faamaonia o le blinking_led.sv file aliali mai i le file lisi.
3. Ina ia fa'amaonia le puna sa'o file mo le fa'atinoga o toe teuteuga, kiliki Poloketi ➤ Fa'aopoopo/Ta'ese files i Poloketi, ma faʻaopoopo le puna lea files mo toe iloiloga o le faatinoga. Afai o iai, aveese le blinking_led.sv mai le lisi o galuega files.
   

   Ifa'atinoga Igoa Toe Iloilo	Punavai File
   blinking_led_empty	blinking_led_empty.sv
   blinking_led_slow	blinking_led_slow.sv

4. Seti le blinking_led_default e pei o le Toe Iloiloga i le taimi nei.
5. Ina ia faʻamaonia le .qdb file e avea ma puna mo root_partition, kiliki Tofiga ➤ Design Partitions Window. Kiliki fa'alua le Vaevaega Fa'amaumauga File cell ma fa'ailoa le blinking_led_static.qdb file.
6. E fa'apena fo'i, fa'ama'oti le blinking_led_supr_partition_final.qdb o le Vaevaega Fa'amaumauga File mo supr_partition.

   Ata 10.I le isi itu, fa'aaoga tofitofiga .qsf nei e fa'amaoti ai le .qdb:
   set_instance_assignment -igoa QDB_FILE_VAEGA \ blinking_led_static.qdb -to |
   set_instance_assignment -igoa QDB_FILE_VAEGA \ emo_le_supr_partition_final.qdb -i le u_top_counter

7. I le Design Partitions Window, kiliki le (...) e sosoo ma le pito pito i luga taumatau koluma ma mafai ai le Entity Re-binding column.

8.  I totonu o le Entity Re-binding cell, faʻamaonia le igoa fou mo le vaega PR o loʻo e suia i le toe iloiloga o loʻo iai nei. Mo le toe iloiloga o le faatinoga o le blinking_led_default, o le igoa o le faalapotopotoga o le blinking_led. I lenei tulaga, o loʻo e faʻauluina le u_blinking_led faʻataʻitaʻiga mai le toe iloiloga faavae tuʻufaʻatasia ma le vaega fou blinking_led. Mo isi toe iloiloga o faʻatinoga, vaʻai i le laulau o loʻo i lalo:

   Toe Iloiloga	Fa'atatau o le toe fusifusia
   blinking_led_slow	blinking_led_slow
   blinking_led_empty	blinking_led_empty

   Ata 11. Fa'amaopoopoina Fa'atasiI le isi itu, e mafai ona e fa'aogaina laina nei i .qsf fa'atonu ta'itasi e seti ai tofiga:
   ##blinking_led_default.qsf
   set_instance_assignment -igoa ENTITY_REBINDING emo_fa'amataina \ -to u_blinking_led
   ##blinking_led_slow.qsf
   set_instance_assignment -igoa ENTITY_REBINDING emo_ta'ita'i_lemu \ -i le u_blinking_led
   ##blinking_led_empty.qsf
   set_instance_assignment -igoa ENTITY_REBINDING blinking_led_empty \ -to u_blinking_led

9. Ave'ese le tusitusiga place_holder mai le Entity Re-binding cell mo supr_partition.
10. Ina ia tuufaatasia le mamanu, kiliki Processing ➤ Start Compilation. I le isi itu, faʻaaoga le poloaiga lenei e faʻapipiʻi ai lenei poloketi: quartus_sh –flow compile blinking_led –c blinking_led_default
11. Toe fai la'asaga 4 e oo i le 11 e saunia ai ma tu'ufa'atasia le fa'atinoga o le blinking_led_slow ma le blinking_led_empty.

1.5.8. Laasaga 8: Suia le SUPR Logic
Ina ia suia le faʻatinoga o le manatu i totonu o le vaeluaga o le SUPR, e tatau ona e suia le puna o le vaeluaga o le SUPR. Fa'auma laasaga nei e sui ai le fa'ata'ita'iga u_top_counter i le vaeluaga o le SUPR ma le vaega pito i luga.counter_fast.

1. Ina ia seti le toe iloiloga o le faatinoga o le SUPR e pei o le taimi nei, kiliki Project ➤ Revisions ma seti impl_blinking_led_supr_new e pei o le toe iloiloga o loʻo iai nei, pe filifili le
   toe iloiloga ile Intel Quartus Prime toolbar.
2. Ina ia fa'amaonia le puna sa'o file mo le toe iloiloga o le faatinoga, kiliki Poloketi ➤
   Faaopoopo/ Aveese files i le Poloketi, ma fa'amaonia o top_counter_fast.sv o le puna lea mo le impl_blinking_led_supr_new toe teuteuga. Afai o iai, aveese top_counter.sv mai le lisi o galuega files.
3. Ina ia faʻamaonia le .qdb file e feso'ota'i ma le vaeluaga o a'a, kiliki Tofiga ➤ Design Partitions Window, ona fa'alua lea ona kiliki le Vaevaega Fa'amaumauga File sela e ta'u mai ai blinking_led_static.qdb.
   I le isi itu, faʻaaoga le poloaiga lenei e tuʻuina atu ai lenei file: set_instance_assignment -igoa QDB_FILE_VAEGA \ blinking_led_static.qdb -to |
4. I totonu o le Entity Re-binding cell mo le pr_partition, faʻamaonia le igoa faʻapitoa talafeagai. Mo lenei example, fa'amaonia le blinking_led_empty entity. I lenei tulaga, o loʻo e faʻauluina le u_blinking_led faʻataʻitaʻiga mai le toe teuteuga faavae tuʻufaʻatasia ma le vaega fou linking_led_empty. Ole laina lea ua iai nei ile .qsf:
   ##impl_blinking_led_supr_new.qsf set_instance_assignment -igoa ENTITY_REBINDING blinking_led_empty \ -to u_blinking_led
5. I totonu o le Entity Re-binding cell mo supr_partition, faʻamaonia le vaega pito i luga_counter_fast. top_counter_fast o le igoa o le static entity e suitulaga i le u_top_counter pe a maeʻa le SUPR.##impl_blinking_led_supr_new.qsf set_instance_assignment -igoa ENTITY_REBINDING top_counter_fast \ -to u_top_counter
6. Ina ia tuufaatasia le mamanu, kiliki Processing ➤ Start Compilation. I le isi itu, faʻaaoga le faʻatonuga e tuʻufaʻatasia ai lenei toe iloiloga o le poloketi: quartus_sh –flow compile blinking_led –c \ impl_blinking_led_supr_new

1.5.9. Laasaga 9: Polokalama le Komiti Faatino
Mulimuli i laasaga nei e faʻafesoʻotaʻi ma faʻapipiʻi le Intel Agilex F-Series FPGA development board.

1. Faʻafesoʻotaʻi le eletise i le Intel Agilex F-Series FPGA development board.
2. Fa'afeso'ota'i se uaea USB i le va o lau PC USB port ma le USB polokalame polokalame i luga o le laupapa atina'e.
3. Tatala le polokalama Intel Quartus Prime, ona kiliki lea o Tools ➤ Programmer. Va'ai ile Polokalama a Komiti Fa'atino.
4. I le Polokalama, kiliki Faʻatonu Setup, ona filifili lea o le USB-Blaster.
5. Kiliki Auto Detect, ona filifili lea o le masini AGFB014R24B.
6.  Kiliki OK. O le Intel Quartus Prime software e iloa ma faʻafouina le Polokalama ma masini FPGA e tolu i luga o le laupapa.
7.  Filifili le masini AGFB014R24B, kiliki Suiga File, ma uta le blinking_led_default.sof file.
8. Fa'aaga le Polokalama/Fa'atonu mo le blinking_led_default.sof file.
9. Kiliki Amata ma faʻatali mo le alualu i luma pa e oʻo i le 100%.
10.  Mata'ituina ia LED i luga o le laupapa e emo.
11. Ina ia fa'apolokalame na'o le PR region, kiliki-matau le blinking_led_default.sof file i le Polokalama ma kiliki Faʻaopoopo PR Programming File. Filifili le blinking_led_slow.pr_partition.rbf file.
12. Fa'agata Polokalama/Configure mo le blinking_led_default.sof file.
13.  Fa'aaga le Polokalama/Configure mo le blinking_led_slow.pr_partition.rbf file, ona kiliki lea Amata. I luga o le laupapa, mata'ituina le LED[0] ma le LED[1] o lo'o fa'aauau pea ona emo. A o'o le pa o le alualu i luma i le 100%, emo fa'agesegese le LED[2] ma le LED[3].
14. Ina ia toe polokalame le PR region, kiliki-matau le .rbf file i le Polokalama, ona kiliki lea Suiga PR Programing File.
15.  Filifili le .rbf files mo isi tagata e lua e matau le amio i luga o le laupapa. Tu'u le blinking_led_default.pr_partition.rbf file mafua ai ona emoe le LED i le taimi muamua, ma utaina le blinking_led_empty.pr_partition.rbf file mafua ai ona tumau pea le LED. 17. Ina ia suia le manatu SUPR, toe fai le laasaga 7 i luga e filifili ai le impl_blinking_led_supr_new.sof. Ina ua uma ona suia lenei file, ta'ita'i [0:1] ua emo nei i se saoasaoa vave nai lo le taimi muamua. O le isi PR .rbf files e fetaui foi ma le .sof fou.
    Fa'aaliga: O le Assembler e gaosia se .rbf file mo le itulagi SUPR. Ae peitai, e le tatau ona e faaaogaina lenei file e toe fa'apolokalame le FPGA i le taimi ta'avale ona o le vaeluaga o le SUPR e le'o fa'atosinaina le alalaupapa fa'aisa, fa'atonu a le PR, ma isi fa'atatau i le faiga atoa. A e faia suiga i le SUPR partition logic, e tatau ona e toe polokalame le .sof atoa file mai le tuufaatasia o toe iloiloga o le faatinoga o le SUPR.

Ata 12. Fa'apolokalameina o se Komiti Fa'atino
1.5.9.1. Fa'afitauli Fa'aletonu o Polokalama a le PR
Faʻamautinoaina le faʻatulagaina lelei o le Intel Quartus Prime Programmer ma meafaigaluega fesoʻotaʻi e fesoasoani e aloese mai soʻo se mea sese i le taimi o polokalame PR.
Afai e te feagai ma soʻo se faʻaletonu polokalame PR, vaʻai i le "Troubleshooting PR Programming Errors" i le Intel Quartus Prime Pro Edition User Guide: Partial Reconfiguration mo fautuaga faʻafitauli i lea laasaga ma lea laasaga.
Fa'amatalaga Fa'atatau

Fa'afitauli Fa'aletonu o Polokalama a le PR

1.5.10. Suia le Vaega o le SUPR
E mafai ona e suia se vaeluaga SUPR o iai. A maeʻa ona suia le vaeluaga SUPR, e tatau ona e faʻapipiʻiina, faʻatupu le .sof file, ma faapolokalame le laupapa, e aunoa ma le tuufaatasia o isi tagata. Mo exampia, mulimuli i laasaga nei e sui ai le top_counter_fast.sv module e faitau vave:

1. Seti impl_blinking_led_supr_new e fai ma toe teuteuga o iai nei.
2.  I le top_counter_fast.sv file, sui le fa'amatalaga count_d + 2 ile count_d + 4.
3.  Fa'atonu tulafono nei e toe fa'aopoopo le poloka SUPR ma fa'atupu le .sof fou file: quartus_sh –fa'agasolo fa'apipi'i fa'apogai_led \ -c impl_blinking_led_supr_new
   O le .sof o lo'o maua nei o lo'o i ai le vaega fou o le SUPR, ma fa'aaoga le blinking_led mo le fa'aletonu (power-on) persona.

1.6. Fa'amatalaga Toe Iloiloga o Fa'amaumauga o le AN 987: Fa'afou Fa'afou Fa'ailoga Fa'atonu Fa'atonu Fa'atonu Fa'asologa Fa'asologa

Fa'amatalaga Fa'amaumauga	Intel Quartus Prime Version	Suiga
2022.10.24	22.	Fa'alauiloa muamua o le pepa.

Fa'afou mo le Intel® Quartus®Prime Design Suite: 22.3

Tali i FAQ pito i luga:

Lauina Manatu

Q O le a le fa'afouga fa'amautu vaega toefa'atonu

Ose Fa'afou Fa'afou Fa'atonu Fa'atonu i le itulau 3

Q O le a le mea ou te manaʻomia mo lenei aʻoaʻoga?

O se A'oa'oga Manaomia ile itulau 3

Q O fea e mafai ona ou maua ai le mamanu faʻasino?

Ose Fa'asinoga Fa'asinoga Lafo Files i le itulau e 5

Q E fa'afefea ona ou faia se mamanu SUPR?

Se Fa'asinomaga Fa'asologa o Fa'asologa i le itulau e 6

Q O le a le PR persona?

Fa'amatala Tagata i le itulau e 10

Q E fa'afefea ona ou suia le manatu ole SUPR? A Suia le SUPR Logic i le itulau 16

A Suia le SUPR Logic i le itulau 16

Q E fa'afefea ona ou fa'apolokalameina le laupapa?

Se Polokalama a le Komiti Faatino i le itulau e 18

Q O a mataupu ma tapula'a ua iloa e le PR?

A Intel FPGA Lagolago Fono: PR

Faʻasinomaga Faʻainitaneti
Lauina Manatu

ID: 749443
AN-987
Fa'aliliuga: 2022.10.24

Pepa / Punaoa

intel Agilex F-Series FPGA Development Board [pdf] Taiala mo Tagata Fa'aoga Agilex F-Series, Agilex F-Series FPGA Development Board, FPGA Development Board, Development Board, Board

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