ALTERA Afa VE FPGA Komiti Fa'atino
Fa'amatalaga o oloa
Fa'amatalaga
- Fa'ata'ita'iga FPGA: Afa VE FPGA (5CEFA7F31I7N)
- FPGA Paket: 896-pin FineLine BGA (FBGA)
- Pule: Foma'i vave fa'atutusa fa'atasi (FPP).
- Fa'ata'ita'iga CPLD: MAX II CPLD (EPM240M100I5N)
- CPLD Paket: 100-pin FBGA
- Uati fa'apolokalame fa'aola mo le fa'aoga uati fa'asino ile FPGA
- 50-MHz oscillator fa'ai'u tasi mo le fa'aoga uati FPGA ma MAX V CPLD
- 100-MHz oscillator tasi fa'ai'uga mo le MAX V CPLD fa'aoga uati fa'atulagaina
- SMA ulufale (LVDS)
- Manatua:
- Lua 256-Mbyte (MB) DDR3 SDRAM masini faʻatasi ma se pasi faʻamaumauga 16-bit
- Tasi 18-Mbit (Mb) SSRAM
- Tasi le 512-Mb emo fa'atasi
- Tasi le 512-MB LPDDR2 SDRAM ma le 32-bit data pasi (na'o le 16-bit data pasi o lo'o fa'aogaina i luga ole laupapa)
- Tasi le 64-Kb I2C fa'asologa e mafai ona tape eletise PROM (EEPROM)
- Fa'ainisinia: 6.5 x 4.5 lapoa laupapa
Fa'atonuga o le Fa'aaogaina o Mea
Mataupu 1: Ua umaview
Fa'amatalaga Lautele
O le Afa VE FPGA Development Board ua mamanuina e tuʻuina atu tomai faʻapitoa faʻataʻitaʻiga faʻatasi ai ma foliga e pei o le toe faʻatulagaina o vaega. E ofoina atu le faʻagaioiga vave, faʻaitiitia le faʻaogaina o le eletise, ma vave le taimi i maketi faʻatusatusa i aiga FPGA muamua.
Sootaga aoga
Mo nisi fa'amatalaga i mataupu nei, va'ai i pepa ta'itasi:
- Aiga o masini a le afa V: Tusitaulima Mea faigaluega a le Afa V
- HSMC faʻamatalaga: High Speed Mezzanine Card (HSMC) Fa'amatalaga
Mataupu 2: Vaega Fa'atonu
Polokalama Vaega Fa'atonu
O le laupapa atina'e o lo'o fa'aalia ai poloka vaega tetele nei:
- Tasi le Afa VE FPGA (5CEFA7F31I7N) ile 896-pin FineLine BGA (FBGA)
- Pule: Fa'apipi'i fa'ata'ita'i fa'atasi (FPP).
- MAX II CPLD (EPM240M100I5N) i se pusa FBGA 100-pin
- Uati fa'apolokalame fa'aola mo le fa'aoga uati fa'asino ile FPGA
- 50-MHz oscillator fa'ai'u tasi mo le fa'aoga uati FPGA ma MAX V CPLD
- 100-MHz oscillator tasi fa'ai'uga mo le MAX V CPLD fa'aoga uati fa'atulagaina
- SMA ulufale (LVDS)
- Manatua:
- Lua 256-Mbyte (MB) DDR3 SDRAM masini faʻatasi ma se pasi faʻamaumauga 16-bit
- Tasi 18-Mbit (Mb) SSRAM
- Tasi le 512-Mb emo fa'atasi
- Tasi le 512-MB LPDDR2 SDRAM ma le 32-bit data pasi (na'o le 16-bit data pasi o lo'o fa'aogaina i luga ole laupapa)
- Tasi le 64-Kb I2C fa'asologa e mafai ona tape eletise PROM (EEPROM)
Fa'ainisinia
O le laupapa atinaʻe e iai le tele o le 6.5 x 4.5 inisi.
Mataupu 3: Fa'asinomaga Vaega a le Komiti Fa'atonu
O lenei vaega o loʻo tuʻuina atu ai faʻamatalaga auiliili e uiga i vaega taʻitasi laupapa ma ona faʻatinoga. Fa'amolemole tagai ile Cyclone VE FPGA Development Board Reference Manual mo nisi fa'amatalaga.
FAQs
F: O fea e mafai ona ou maua ai HSMC lata mai o lo'o avanoa?
A: Ina ia va'ai i se lisi o HSMC aupito lata mai o lo'o avanoa pe la'u mai se kopi o fa'amatalaga HSMC, va'ai i le Development Board Daughtercards page o le Altera. webnofoaga.
Q: O le a le advantago le Komiti Fa'atino o Atiina'e a le Afa VE FPGA?
A: O le Cyclone VE FPGA Development Board e ofoina atu le alualu i luma o mamanu ma faʻafouga, e pei o le toe faʻaleleia o vaega, e faʻamautinoa ai le faʻagaioiina vave, faʻaitiitia le faʻaogaina o le eletise, ma le televave o le taimi i maketi pe a faʻatusatusa i aiga FPGA muamua.
F: O fea e mafai ona ou maua ai nisi fa'amatalaga e uiga i le aiga masini o le Afa V?
A: Mo nisi fa'amatalaga e uiga i le aiga masini o le Afa V, va'ai i le Tusitaulima Meafaitino a le Afa V.
Q: O le a le tele o le laupapa atinaʻe?
A: O le laupapa atinae o loʻo i ai le tele o 6.5 x 4.5 inisi.
101 Drive Faʻaleleia
San Jose, CA 95134
www.altera.com
MNL-01075-1.4
© 2017 Altera Corporation. Ua taofia aia tatau uma. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS ma STRATIX upu ma logos o faailoga tau fefaatauaiga a Altera Corporation ma faamauina i le US Patent and Trademark Office ma isi atunuu. O isi upu uma ma tagavai ua fa'ailoaina o fa'ailoga tau fefa'ataua'iga po'o fa'ailoga tautua o meatotino a latou tagata e umia e pei ona fa'amatalaina i le www.altera.com/common/legal.html. Altera e fa'amaonia le fa'atinoina o ana oloa semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'amaonia masani a Altera, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. Altera e leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se tusitusiga e Altera. Altera tagata fa'atau e fautuaina ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga lolomi ma a'o le'i tu'uina atu oka mo oloa po'o tautua.
Aukuso 2017 Altera Corporation Afa VE FPGA Komiti Atina'e
Tusi Taiala
O lenei pepa o lo'o fa'amatalaina ai mea faigaluega o le Cyclone® VE FPGA development board, e aofia ai fa'amatalaga auiliili o pine-out ma vaega fa'asinomaga e mana'omia e fai ai fa'ata'ita'iga masani FPGA e feso'ota'i ma vaega uma o le laupapa.
Ua umaview
Fa'amatalaga Lautele
O le Afa VE FPGA komiti fa'atupuina e tu'uina atu se fa'avae meafaigaluega mo le atina'eina ma le fa'ata'ita'iina o fa'ata'ita'iga e maualalo le malosi, fa'atinoina, ma fa'aoga fa'atatau e fa'aoga ai le Altera's Cyclone VE FPGA. O lo'o tu'uina atu e le laupapa le tele o feso'ota'iga ma mea e manatua e fa'afaigofie ai le atina'eina o ata o le Afa VE FPGA. E tasi le feso'ota'iga kata mezzanine maualuga (HSMC) e avanoa e fa'aopoopo ai galuega fa'aopoopo e ala i HSMC eseese e maua mai le Altera® ma pa'aga eseese.
- Ina ia va'ai i se lisi o HSMC lata mai o lo'o avanoa pe la'u mai se kopi o fa'amatalaga HSMC, va'ai i le itulau o Fa'atonu a le Komiti Fa'atino a le Atina'e o le Altera. webnofoaga.
Fuafuaga alualu i luma ma faafouga, e pei o se vaega toe fetuutuunai, ia mautinoa o mamanu faatino i le Afa VE FPGAs galue vave, ma le paoa maualalo, ma e sili atu le taimi e maketi ai nai lo aiga FPGA muamua. - Mo nisi fa'amatalaga i mataupu nei, va'ai i pepa ta'itasi:
- Aiga o masini a le Afa V, tagai i le Tusitaulima Mea faigaluega a le Afa V.
- Fa'amatalaga HSMC, fa'asino ile High Speed Mezzanine Card (HSMC) Fa'amatalaga.
Polokalama Vaega Fa'atonu
O le laupapa atina'e o lo'o fa'aalia ai poloka vaega tetele nei:
- Tasi le Afa VE FPGA (5CEFA7F31I7N) i totonu ole afifi 896-pin FineLine BGA (FBGA)
- 149,500 LEs
- 56,480 fetuutuuna'i fa'aoga fa'aoga (ALM)
- 6,860 Kbit (Kb) M10K ma le 836 Kb MLAB manatua
- E fitu vaega ninii loka loka (PLLs)
- 312 18x18-bit fa'atele
- 480 fa'amoemoe lautele fa'aoga/tuuina atu (GPIO)
- 1.1-V autu voltage
- FPGA fa'asologa o feso'ota'iga
- Fa'atonu Fa'asologa (AS) x1 po'o le AS x4 (EPCQ256SI16N)
- MAX® V CPLD (5M2210ZF256I5N) i totonu o se pusa FBGA 256-pin e fai ma Pule Fa'atonu.
- Foma'i vave fa'atutusa fa'atasi (FPP).
- MAX II CPLD (EPM240M100I5N) i totonu o se pusa FBGA 100-pin o se vaega o le USB-BlasterTM II faʻapipiʻi mo le faʻaogaina ma le Quartus® II Programmer
- Si'osi'omaga uati
- Uati fa'apolokalame fa'aola mo le fa'aoga uati fa'asino ile FPGA
- 50-MHz oscillator fa'ai'u tasi mo le fa'aoga uati FPGA ma MAX V CPLD
- 100-MHz oscillator tasi fa'ai'uga mo le MAX V CPLD fa'aoga uati fa'atulagaina
- SMA ulufale (LVDS)
- Manatu
- Lua 256-Mbyte (MB) DDR3 SDRAM masini faʻatasi ma se pasi faʻamaumauga 16-bit
- Tasi 18-Mbit (Mb) SSRAM
- Tasi le 512-Mb emo fa'atasi
- Tasi le 512-MB LPDDR2 SDRAM ma le 32-bit data pasi (na'o le 16-bit data pasi o lo'o fa'aogaina i luga ole laupapa)
- Tasi le 64-Kb I2C fa'asologa e mafai ona tape eletise PROM (EEPROM)
- Fa'aoga lautele fa'aoga/tuuina atu
- LED ma fa'aaliga
- E fa fa'aoga LED
- Tasi fa'atonuga uta LED
- E tasi le faatulagaga ua faia LED
- Tasi mea sese LED
- E tolu fetuutuunaiga filifilia LED
- Fa fa'apipi'i USB-Blaster II tulaga LED
- E tolu HSMC fa'aoga LED
- Sefulu Ethernet LEDs
- E lua fa'amaumauga UART e tu'uina atu ma maua ai fa'amalama
- Lua USB-UART fa'aoga TX / RX LED
- Tasi le mana ile LED
- Tasi fa'aaliga LCD mataitusi lua laina
- Tulei faʻamau
- E tasi le CPU toe setiina oomi ki
- E tasi le MAX V toe fa'amauina fa'amau fa'amau
- E tasi le polokalame e filifili ai le faamau oomi
- E tasi le faamau o le fetuutuunaiga o polokalame
- Fa fa'aoga masani fa'aoga fa'amau
- DIP sui
- Fa MAX V CPLD System Controller ki fa'atonuga
- Lua JTAG filifili filifili DIP ki
- E tasi le ki e pulea DIP ki
- E fa sui fa'aoga DIP lautele
- Paoa sapalai
14–20-V (laptop) DC fa'aoga - Fa'ainisinia
6.5" x 4.5" lapoa laupapa
Fuafuaga poloka a le Komiti Atina'e
Ata 1–1 o lo'o fa'aalia ai se poloka poloka o le laupapa atina'e a le Afa VE FPGA.
Taulimaina o le Komiti Faatino
Pe a tagofia le laupapa, e taua le mataituina o le fa'atonuga fa'aletonu o lo'o i lalo:
fa'aeteete
A aunoa ma le taulimaina lelei o le anti-static, e mafai ona faaleagaina le laupapa. O le mea lea, fa'aaoga puipuiga fa'asaga i le tagofiaina pe a pa'i i le laupapa.
Vaega Komiti
O lenei mataupu o loʻo faʻaalia ai vaega tetele o le Afa VE FPGA komiti atinaʻe. O le Ata 2-1 o lo'o fa'aalia ai nofoaga o lo'o tu'uina atu ai ma le Siata 2-1 o lo'o maua ai se fa'amatalaga puupuu o vaega uma o le laupapa.
Se seti atoatoa o sikola, se faʻamaumauga faʻatulagaina faaletino, ma GERBER files mo le komiti o atina'e o lo'o nofo i totonu o le Afa VE FPGA fa'amaumauga o pusa atia'e pepa.
Mo fa'amatalaga e uiga i le fa'aola o le laupapa ma fa'apipi'i le polokalama fa'ata'ita'iga, tagai ile Cyclone VE FPGA Development Kit User Guide.
O lenei mataupu e aofia ai vaega nei:
- “Lua Fonoview”
- “Measini Fa'apitoa: Afa VE FPGA” i le itulau 2–4
- “MAX V CPLD 5M2210 System Controller” i le itulau 2–5
- “FPGA Configuration” i le itulau 2–10
- “O le Uati” i le itulau 2–18
- “Tulaga Lautele a Tagata Fa'aoga/Galue” i le itulau 2–20
- “Vaega ma Fesootaiga” i le itulau 2–24
- “Manatua” i le itulau 2–32
- “Sapalai Malosiaga” i le itulau 2–41
Avatu le Fonoview
O lenei vaega o loʻo tuʻuina atu se faʻaopoopogaview o le Cyclone VE FPGA development board, e aofia ai se ata o le laupapa fa'amatalaga ma fa'amatalaga vaega. O le ata 2–1 o lo'o fa'aalia ai se fa'aumaview o foliga o le laupapa.
Siata 2-1 o loʻo faʻamatalaina ai vaega ma lisi a latou faʻamatalaga laupapa tutusa.
Laulau 2–1. Vaega Fa'atonu (Vaega 1 o le 3)
| Komiti Fa'atonu Fa'asinomaga | Ituaiga | Fa'amatalaga |
| Fa'aalia Meafaigaluega | ||
| U1 | FPGA | Afa VE FPGA, 5CEFA7F31I7N, 896-pin FBGA. |
| U13 | CPLD | MAX V CPLD, 5M2210ZF256I5N, 256-pin FBGA. |
| Fa'atonuga, Tulaga, ma Seti Elemene | ||
| J4 | JTAG ulutala filifili | Tuuina atu avanoa i le JTAG filifili ma fa'amalo le USB-Blaster II fa'apipi'i pe a fa'aogaina se uaea USB-Blaster fafo. |
| SW2 | JTAG filifili filifili DIP ki | Aveese pe fa'aofi masini i le JTAG filifili. |
| J10 | USB ituaiga-B so'oga | Fa'aoga USB mo polokalame FPGA ma le fa'apipi'iina e ala ile USB-Blaster II JTAG e ala i se uaea USB ituaiga-B. |
Laulau 2–1. Vaega Fa'atonu (Vaega 2 o le 3)
| Komiti Fa'atonu Fa'asinomaga | Ituaiga | Fa'amatalaga |
|
SW3 |
Fa'atonu a le komiti sui DIP |
Puleaina le MAX V CPLD 5M2210 System Controller galuega e pei ole uati e mafai ai, le fa'aogaina o le uati SMA, ma po'o le fea ata e utaina mai le flash memory ile power-up. |
| SW1 | MSEL DIP ki | Pulea le polokalame fa'atulagaina i luga o le laupapa. MSEL pine 0, 1, 2 ma le 4 e feso'ota'i i le DIP ki a'o MSEL pine 3 e feso'ota'i ile eleele. |
| S2 | Polokalama filifili kiliki faamau | Toggles le polokalame filifili LEDs, lea e filifilia le ata o le polokalame e uta mai le flash memory i le FPGA. |
| S1 | Fa'amau fa'atonu polokalame | Uta ata mai le flash memory i le FGPA faʻavae i luga o faʻatulagaga o le polokalame filifilia LED. |
| D19 | Fa'atonuga faia LED | E susulu pe a fa'atulagaina le FPGA. |
| D18 | Uta LED | E fa'amalamalamaina pe a fa'agaoioia e le MAX V CPLD 5M2210 System Controller le FPGA. |
| D17 | Sese LED | E susulu pe a le manuia le fa'atulagaina o le FPGA mai le flash memory. |
| D35 | Mana o le Mana | E susulu pe a iai le mana 5.0-V. |
|
O25 ~ D27 |
Polokalama filifili LED |
Fa'amumuina e fa'aalia ai le fa'asologa o le LED e iloa ai po'o fea ata fa'afoma'i e uta i le FPGA pe a e oomiina le fa'apolokalame filifili fa'amau fa'amau. Va'ai ile Laulau 2–6 mo fa'atulagaga o le LED. |
| O1 ~ D10 | fa'amalama Ethernet | E fa'amalamalama e fa'aalia ai le saoasaoa o feso'ota'iga fa'apea fo'i le fa'asalalauina pe maua le gaioiga. |
| D20, D21 | HSMC uafu LEDs | E mafai ona e fa'atulagaina nei LED e fa'ailoa ai le felauaiga pe maua le gaioiga. |
| D22 | HSMC uafu o loʻo iai LED | E susulu pe a fa'apipi'i se tama teine i le uafu HSMC. |
| D15, D16 | USB-UART LED | E fa'amalamalama pe a fa'aogaina le transmitter USB-UART ma le receiver. |
| D23, D24 | UART fa'asologa | E susulu pe a fa'aogaina le transmitter ma le receiver UART. |
| Uati Itumalo | ||
|
X1 |
Oscillator e mafai ona fa'apolokalameina |
Oscillator e mafai ona fa'apolokalame fa'atasi ma alaleo fa'aletonu o le 125 MHz. E mafai ona fa'apolokalameina le fa'asologa e fa'aaoga ai le GUI fa'atonutonu uati o lo'o fa'agaoioi ile MAX V CPLD 5M2210 System Controller. |
| U4 | 50-MHz oscillator | 50.000-MHz oscillator tioata mo manatu fa'amoemoe lautele. |
| X3 | 100-MHz oscillator | 100.000-MHz oscillator tioata mo le MAX V CPLD 5M2210 System Controller. |
| J2, J3 | So'oga SMA fa'aoga uati | Tu'u mea fa'aoga uati e fetaui ma le LVDS i totonu o le fa'apipi'i tele o le uati. |
| J4 | So'oga SMA fa'aola uati | Tu'u ese 2.5-V CMOS uati fa'asolo mai le FPGA. |
| lautele Tagata fa'aoga Ulufale/Auga | ||
| O28 ~ D31 | LED fa'aoga | E fa fa'aoga LED. E susulu pe a ave maualalo. |
| SW3 | Su'e DIP fa'aoga | Su'e DIP fa'aoga fa'afa. A ON le ki, ua filifilia se manatu 0. |
| S4 | PPU toe setiina oomi faamau | Toe seti le manatu FPGA. |
| S3 | MAX V toe setiina le faamau | Toe setiina le MAX V CPLD 5M2210 System Controller. |
| S5~S8 | Fa'amau fa'aoga fa'aoga fa'amau | Fa fa'aoga fa'aoga fa'amau. Tu'u maualalo pe a oomi. |
| Manatu Meafaigaluega | ||
| U7, U8 | DDR3 x32 manatua | Lua 256-MB DDR3 SDRAM faʻatasi ma se pasi faʻamaumauga 16-bit. |
| U9 | LPDDR2 x 16 manatua | 512-MB LPDDR 2 SDRAM faʻatasi ma le 32-bit pasi, naʻo le 16-bit pasi e faʻaaogaina i luga o lenei laupapa. |
Laulau 2–1. Vaega Fa'atonu (Vaega 3 o le 3)
| Komiti Fa'atonu Fa'asinomaga | Ituaiga | Fa'amatalaga |
| U10 | Flash x16 manatua | 512-Mb masini moli faʻatasi ma se pasi faʻamaumauga 16-bit mo le manatua e le faʻafefe. |
| U11 | SSRAM x16 manatua | 18-Mb masani synchronous RAM ma le 12-bit data pasi ma 4-bit parity. |
| U12 | EEPROM | 64-Mb I2C faasologa EEPROM. |
| Fesootaiga Taulaga | ||
| J1 | HSMC uafu | Tuuina atu 84 CMOS poʻo 17 LVDS auala ile HSMC faʻamatalaga. |
|
J11 |
Gigabit Ethernet taulaga |
RJ-45 feso'ota'iga lea e maua ai se feso'ota'iga Ethernet 10/100/1000 e ala ile Marvell 88E1111 PHY ma le fa'aogaina ole Altera Triple Speed Ethernet MegaCore ole FPGA ile RGMII mode. |
| J12 | Tau UART fa'asologa | DSUB 9-pin connector ma RS-232 transceiver e faatino RS-232 serial UART auala. |
| J13 | USB-UART uafu | Feso'ota'iga USB ma alalaupapa USB-i-UART mo feso'ota'iga UART. |
| J15, J16 | Debug ulutala | Lua 2×8 ulutala mo fa'amoemoega debug. |
| Vitio ma Fa'aaliga Taulaga | ||
| J14 | amio LCD | Feso'ota'i e fa'afeso'ota'i i se fa'ailoga 16 amio × 2 laina LCD module fa'atasi ai ma fa'amaufa'ailoga se lua. |
| Malosiaga Sapalai | ||
| J17 | DC fa'aoga Jack | Talia se sapalai eletise 14–20-V DC. |
| SW5 | Kisi eletise | Su'e i le eletise i luga pe tape le laupapa pe a sau le eletise mai le DC input jack. |
Mea Fa'apitoa: Afa VE FPGA
O le Cyclone VE FPGA development board o lo'o fa'aalia ai se masini Cyclone VE FPGA 5CEFA7F31I7N (U1) i totonu ole afifi FBGA 896-pin.
Mo nisi fa'amatalaga e uiga i le aiga masini a le Afa V, tagai i le Tusitaulima Meafaitino a le Afa V.
Siata 2–2 o lo'o fa'amatala mai ai uiga o le Afa VE FPGA 5CEFA7F31I7N masini.
Laulau 2–2. Afa VE FPGA Vaega
| ALM | E tutusa LEs | M10K RAM Poloka | Aofa'iga RAM (Kbits) | 18-bit × 18-bit Fa'atele | PLLs | afifi Ituaiga |
| 56,480 | 149,500 | 6,860 | 836 | 312 | 7 | 896-pin FBGA |
I/O Punaoa
Ole masini ole Afa VE FPGA 5CEFA7F31I7N e 480 tagata fa'aoga I/Os. Siata 2–3 o lo'o lisiina ai le numera o pine a le Afa VE FPGA I/O ma le fa'aogaina e ala i galuega i luga o le laupapa.
Laulau 2–3. Faitauga o Pin I/O Afa VE FPGA
| Galuega | I/O Tulaga | I/O Faitau | Fa'apitoa pine |
| DDR3 | 1.5-V SSTL | 71 | Tasi le eseesega x4 DQS pine |
| LPDDR2 | 1.2-V HSUL | 37 | Tasi le eseesega x2 DQS pine |
| Flash, SSRAM, EEPROM, ma MAX V
pasi FSM |
2.5-V CMOS, 3.3-V LVCMOS | 69 | — |
| HSMC uafu | 2.5-V CMOS + LVDS | 79 | 17 LVDS, I2C |
| Gigabit Ethernet taulaga | 2.5-V CMOS | 42 | — |
| Fa'apipi'i USB-Blaster II | 2.5-V CMOS | 20 | — |
| Ulutala Debug | 1.5-V, 2.5-V | 20 | — |
| UART | 3.3-V LVTTL | 4 | — |
| USB-UART | 2.5-V CMOS | 12 | — |
| Tulei faʻamau | 2.5-V CMOS | 5 | Tasi DEV_CLRn pine |
| DIP sui | 2.5-V CMOS | 4 | — |
| amio LCD | 2.5-V CMOS | 11 | — |
| LED | 2.5-V CMOS | 9 | — |
| Uati po'o Oscillators | 2.5-V CMOS + LVDS | 12 | E tasi le pine uati i fafo |
| Aofa'iga I/O Fa'aaogaina: | 395 | ||
MAX V CPLD 5M2210 Pule Fa'atonu
E fa'aogaina e le Komiti Fa'atonu le 5M2210 System Controller, o le Altera MAX V CPLD, mo fa'amoemoega nei:
- Fa'atonuga FPGA mai moli
- Fuaina o le malosi
- Pulea ma le resitalaina o tulaga mo le fa'afouga mamao
Ata 2–2 o lo'o fa'aalia ai le MAX V CPLD 5M2210 System Controller le fa'atinoina ma feso'ota'iga va'ava'ai fafo e pei o se poloka poloka.\
Ata 2–2. MAX V CPLD 5M2210 Fa'atonu Fa'atonu Poloka Ata
Laulau 2–4 o lo'o lisiina ai fa'ailoga I/O o lo'o iai ile MAX V CPLD 5M2210 System Controller. O igoa fa'ailoga ma galuega e fa'atatau ile masini MAX V.
E mafai ona e sii maia se example mamanu ma pine nofoaga ma tofiga ua maeʻa e tusa ai ma le laulau o loʻo i lalo mai le Altera Design Store. I le Cyclone VE FPGA Development Kit, i lalo ole Design Examples, kiliki Afa VE FPGA Development Kit Baseline Pinout.
Laulau 2–4. MAX V CPLD 5M2210 Fa'atonu Fa'atonu Mea Fa'apipi'i (Vaega 1 o le 5)
| Komiti Fa'atonu Fa'asinoga (U13) | Fuafuaga Fa'ailoga Igoa | I/O Tulaga | Fa'amatalaga |
| N4 | 5M2210_JTAG_TMS | 3.3-V | MAX VJTAG TMS |
| E9 | CLK50_EN | 2.5-V | 50 MHz oscillator mafai |
| H12 | CLK_CONFIG | 2.5-V | 100 MHz fetuutuunaiga uati ulufale |
| A15 | CLK_ENABLE | 2.5-V | DIP ki mo le uati oscillator mafai |
| A13 | CLK_SEL | 2.5-V | DIP ki mo le uati filifilia—SMA po'o le oscillator |
| J12 | CLKIN_50_MAXV | 2.5-V | 50 MHz fa'aoga uati |
| D9 | CLOCK_SCL | 2.5-V | Uati oscillator I2C polokalame |
| C9 | CLOCK_SDA | 2.5-V | Faʻamatalaga oscillator I2C faʻapipiʻiina |
| D10 | CPU_RESETN | 2.5-V | FPGA toe setiina oomi faamau |
| P12 | EXTRA_SIG0 | 2.5-V | Fa'apipi'i USB-Blaster II fa'aoga. Fa'apolopolo mo le fa'aoga i le lumana'i |
| T13 | EXTRA_SIG1 | 2.5-V | Fa'apipi'i USB-Blaster II fa'aoga. Fa'apolopolo mo le fa'aoga i le lumana'i |
| T15 | EXTRA_SIG2 | 2.5-V | Fa'apipi'i USB-Blaster II fa'aoga. Fa'apolopolo mo le fa'aoga i le lumana'i |
| A2 | FACTORY_LOAD | 2.5-V | DIP sui e uta falegaosimea po'o le fa'aoga fa'aoga ile fa'aola |
Laulau 2–4. MAX V CPLD 5M2210 Fa'atonu Fa'atonu Mea Fa'apipi'i (Vaega 2 o le 5)
| Komiti Fa'atonu Fa'asinoga (U13) | Fuafuaga Fa'ailoga Igoa | I/O Tulaga | Fa'amatalaga |
| R14 | FACTORY_REQUEST | 2.5-V | Faʻapipiʻi USB-Blaster II talosaga e lafo le faʻatonuga FACTORY |
| N12 | FACTORY_STATUS | 2.5-V | Fa'apipi'i USB-Blaster II FACTORY tulaga fa'atonuga |
| C8 | FAN_FORCE_ON | 2.5-V | DIP ki i luga pe tape le ili |
| N7 | FLASH_ADVN | 2.5-V | FSM pasi flash manatua tuatusi aoga |
| R5 | FLASH_CEN | 2.5-V | FSM pasi flash memory chip mafai |
| R6 | FLASH_CLK | 2.5-V | Uati manatua moli FSM pasi |
| M6 | FLASH_OEN | 2.5-V | FSM pasi flash manatua mea e mafai ai |
| T5 | FLASH_RDYBSYN | 2.5-V | FSM pasi flash manatua ua saunia |
| P7 | FLASH_RESETN | 2.5-V | Toe setiina le manatua o le flash pasi FSM |
| N6 | FLASH_WEN | 2.5-V | FSM pasi flash manatua tusitusi mafai |
| K1 | FPGA_CONF_FAIA | 3.3-V | FPGA fetuutuunai faia LED |
| D3 | FPGA_CONFIG_D0 | 3.3-V | FPGA faʻamaumauga faʻatulagaina |
| C2 | FPGA_CONFIG_D1 | 3.3-V | FPGA faʻamaumauga faʻatulagaina |
| C3 | FPGA_CONFIG_D2 | 3.3-V | FPGA faʻamaumauga faʻatulagaina |
| E3 | FPGA_CONFIG_D3 | 3.3-V | FPGA faʻamaumauga faʻatulagaina |
| D2 | FPGA_CONFIG_D4 | 3.3-V | FPGA faʻamaumauga faʻatulagaina |
| E4 | FPGA_CONFIG_D5 | 3.3-V | FPGA faʻamaumauga faʻatulagaina |
| D1 | FPGA_CONFIG_D6 | 3.3-V | FPGA faʻamaumauga faʻatulagaina |
| E5 | FPGA_CONFIG_D7 | 3.3-V | FPGA faʻamaumauga faʻatulagaina |
| F3 | FPGA_CONFIG_D8 | 3.3-V | FPGA faʻamaumauga faʻatulagaina |
| E1 | FPGA_CONFIG_D9 | 3.3-V | FPGA faʻamaumauga faʻatulagaina |
| F4 | FPGA_CONFIG_D10 | 3.3-V | FPGA faʻamaumauga faʻatulagaina |
| F2 | FPGA_CONFIG_D11 | 3.3-V | FPGA faʻamaumauga faʻatulagaina |
| F1 | FPGA_CONFIG_D12 | 3.3-V | FPGA faʻamaumauga faʻatulagaina |
| F6 | FPGA_CONFIG_D13 | 3.3-V | FPGA faʻamaumauga faʻatulagaina |
| G2 | FPGA_CONFIG_D14 | 3.3-V | FPGA faʻamaumauga faʻatulagaina |
| G3 | FPGA_CONFIG_D15 | 3.3-V | FPGA faʻamaumauga faʻatulagaina |
| K4 | FPGA_MAX_DCLK | 3.3-V | FPGA fetuutuunaiga uati |
| J3 | FPGA_DCLK | 3.3-V | FPGA fetuutuunaiga uati |
| N1 | FPGA_NCONFIG | 3.3-V | Fa'atonu FPGA o lo'o galue |
| J4 | FPGA_NSTATUS | 3.3-V | FPGA faatulagaga sauni |
| H1 | FPGA_PR_FAIA | 3.3-V | FPGA vaega toe fetuutuunai faia |
| P2 | FPGA_PR_ERROR | 3.3-V | FPGA vaega toe fetuutuunai sese |
| E2 | FPGA_PR_SAUNI | 3.3-V | FPGA vaega toe fetuutuunai sauni |
| F5 | FPGA_PR_REQUEST | 3.3-V | FPGA talosaga toe fetuutuunai vaega |
| L5 | FPGA_MAX_NCS | 3.3-V | FPGA fetuutuunaiga chip filifili |
| E14 | FSM_A1 | 2.5-V | FSM tuatusi pasi |
| C14 | FSM_A2 | 2.5-V | FSM tuatusi pasi |
Laulau 2–4. MAX V CPLD 5M2210 Fa'atonu Fa'atonu Mea Fa'apipi'i (Vaega 3 o le 5)
| Komiti Fa'atonu Fa'asinoga (U13) | Fuafuaga Fa'ailoga Igoa | I/O Tulaga | Fa'amatalaga |
| C15 | FSM_A3 | 2.5-V | FSM tuatusi pasi |
| E13 | FSM_A4 | 2.5-V | FSM tuatusi pasi |
| E12 | FSM_A5 | 2.5-V | FSM tuatusi pasi |
| D15 | FSM_A6 | 2.5-V | FSM tuatusi pasi |
| F14 | FSM_A7 | 2.5-V | FSM tuatusi pasi |
| D16 | FSM_A8 | 2.5-V | FSM tuatusi pasi |
| F13 | FSM_A9 | 2.5-V | FSM tuatusi pasi |
| E15 | FSM_A10 | 2.5-V | FSM tuatusi pasi |
| E16 | FSM_A11 | 2.5-V | FSM tuatusi pasi |
| F15 | FSM_A12 | 2.5-V | FSM tuatusi pasi |
| G14 | FSM_A13 | 2.5-V | FSM tuatusi pasi |
| F16 | FSM_A14 | 2.5-V | FSM tuatusi pasi |
| G13 | FSM_A15 | 2.5-V | FSM tuatusi pasi |
| G15 | FSM_A16 | 2.5-V | FSM tuatusi pasi |
| G12 | FSM_A17 | 2.5-V | FSM tuatusi pasi |
| G16 | FSM_A18 | 2.5-V | FSM tuatusi pasi |
| H14 | FSM_A19 | 2.5-V | FSM tuatusi pasi |
| H20 | FSM_A20 | 2.5-V | FSM tuatusi pasi |
| H13 | FSM_A21 | 2.5-V | FSM tuatusi pasi |
| H16 | FSM_A22 | 2.5-V | FSM tuatusi pasi |
| J13 | FSM_A23 | 2.5-V | FSM tuatusi pasi |
| J16 | FSM_A24 | 2.5-V | FSM tuatusi pasi |
| T2 | FSM_A25 | 2.5-V | FSM tuatusi pasi |
| P5 | FSM_A26 | 2.5-V | FSM tuatusi pasi |
| J14 | FSM_D0 | 2.5-V | pasi fa'amaumauga FSM |
| J15 | FSM_D1 | 2.5-V | pasi fa'amaumauga FSM |
| K16 | FSM_D2 | 2.5-V | pasi fa'amaumauga FSM |
| K13 | FSM_D3 | 2.5-V | pasi fa'amaumauga FSM |
| K15 | FSM_D4 | 2.5-V | pasi fa'amaumauga FSM |
| K14 | FSM_D5 | 2.5-V | pasi fa'amaumauga FSM |
| L16 | FSM_D6 | 2.5-V | pasi fa'amaumauga FSM |
| L11 | FSM_D7 | 2.5-V | pasi fa'amaumauga FSM |
| L15 | FSM_D8 | 2.5-V | pasi fa'amaumauga FSM |
| L12 | FSM_D9 | 2.5-V | pasi fa'amaumauga FSM |
| M16 | FSM_D10 | 2.5-V | pasi fa'amaumauga FSM |
| L13 | FSM_D11 | 2.5-V | pasi fa'amaumauga FSM |
| M15 | FSM_D12 | 2.5-V | pasi fa'amaumauga FSM |
| L14 | FSM_D13 | 2.5-V | pasi fa'amaumauga FSM |
| N16 | FSM_D14 | 2.5-V | pasi fa'amaumauga FSM |
Laulau 2–4. MAX V CPLD 5M2210 Fa'atonu Fa'atonu Mea Fa'apipi'i (Vaega 4 o le 5)
| Komiti Fa'atonu Fa'asinoga (U13) | Fuafuaga Fa'ailoga Igoa | I/O Tulaga | Fa'amatalaga |
| M13 | FSM_D15 | 2.5-V | pasi fa'amaumauga FSM |
| B8 | HSMA_PRSNTN | 2.5-V | HSMC uafu o lo'o iai |
| L6 | JTAG_5M2210_TDI | 3.3-V | MAX V CPLD JTAG fa'amatalaga filifili i totonu |
| M5 | JTAG_5M2210_TDO | 3.3-V | MAX V CPLD JTAG fa'amatalaga filifili i fafo |
| P3 | JTAG_TCK | 3.3-V | JTAG uati filifili |
| P11 | M570_CLOCK | 2.5-V | 25-MHz uati i faʻapipiʻi USB-Blaster II mo le auina atu o le faʻatonuga FACTORY |
| M1 | M570_JTAG_EN | 3.3-V | Fa'ailoga maualalo e fa'amalo ai le USB-Blaster II |
| P10 | MAX5_BEN0 | 2.5-V | FSM pasi MAX V byte mafai 0 |
| R11 | MAX5_BEN1 | 2.5-V | FSM pasi MAX V byte mafai 1 |
| T12 | MAX5_BEN2 | 2.5-V | FSM pasi MAX V byte mafai 2 |
| N11 | MAX5_BEN3 | 2.5-V | FSM pasi MAX V byte mafai 3 |
| T11 | MAX5_CLK | 2.5-V | FSM pasi MAX V uati |
| R10 | MAX5_CSN | 2.5-V | FSM pasi MAX V chip filifili |
| M10 | MAX5_OEN | 2.5-V | FSM pasi MAX V fa'aagaoioiga |
| N10 | MAX5_WEN | 2.5-V | FSM pasi MAX V tusi mafai |
| E11 | MAX_CONF_DONEN | 2.5-V | Fa'apipi'i USB-Blaster II fa'atulagaina fa'atino LED |
| A4 | MAX_ERROR | 2.5-V | FPGA fetuutuunaiga sese LED |
| A6 | MAX_LOAD | 2.5-V | FPGA fetuutuunai LED galue |
| M9 | MAX_RESETN | 2.5-V | MAX V toe setiina le faamau |
| B7 | OVERTEMP | 2.5-V | E mafai e le ili mata'ituina le vevela |
| D12 | PGM_CONFIG | 2.5-V | U'u le ata fa'amalama e iloa mai e PGM LEDs |
| B14 | PGM_LED0 | 2.5-V | Flash memory PGM filifili faailoga 0 |
| C13 | PGM_LED1 | 2.5-V | Flash memory PGM filifili faailoga 1 |
| B16 | PGM_LED2 | 2.5-V | Flash memory PGM filifili faailoga 2 |
| B13 | PGM_SEL | 2.5-V | Su'e le fa'asologa o le PGM_LED[2:0] LED |
| H4 | PSAS_CSn | 3.3-V | AS fetuutuunaiga chip filifili |
| G1 | PSAS_DCLK | 3.3-V | AS fetuutuunaiga uati |
| G4 | PSAS_CONF_FAIA | 3.3-V | AS fa'atulagaina ua mae'a |
| H2 | PSAS_CONFIGn | 3.3-V | AS fa'atulagaina fa'agaoioi |
| G5 | PSAS_DATA1 | 3.3-V | AS fa'amaumauga fa'atulagaina |
| H3 | PSAS_DATA0_ASD0 | 3.3-V | AS fa'amaumauga fa'atulagaina |
| J1 | PSAS_CEn | 3.3-V | AS fetuutuunaiga chip mafai |
| R12 | SECURITY_MODE | 2.5-V | DIP ki mo le USB-Blaster II fa'apipi'i e tu'uina atu le fa'atonuga FACTORY i luga |
| E7 | SENSE_CS0N | 2.5-V | Pule mataitu pusi filifili |
| A5 | SENSE_SCK | 2.5-V | Uati mataitu SPI mana |
| D7 | SENSE_SDI | 2.5-V | Mataitu eletise SPI faʻamaumauga i totonu |
| B6 | SENSE_SDO | 2.5-V | Malosiaga mata'itu fa'amatalaga SPI |
Laulau 2–4. MAX V CPLD 5M2210 Fa'atonu Fa'atonu Mea Fa'apipi'i (Vaega 5 o le 5)
| Komiti Fa'atonu Fa'asinoga (U13) | Fuafuaga Fa'ailoga Igoa | I/O Tulaga | Fa'amatalaga |
| M13 | FSM_D15 | 2.5-V | pasi fa'amaumauga FSM |
| B8 | HSMA_PRSNTN | 2.5-V | HSMC uafu o lo'o iai |
| L6 | JTAG_5M2210_TDI | 3.3-V | MAX V CPLD JTAG fa'amatalaga filifili i totonu |
| M5 | JTAG_5M2210_TDO | 3.3-V | MAX V CPLD JTAG fa'amatalaga filifili i fafo |
| P3 | JTAG_TCK | 3.3-V | JTAG uati filifili |
| P11 | M570_CLOCK | 2.5-V | 25-MHz uati i faʻapipiʻi USB-Blaster II mo le auina atu o le faʻatonuga FACTORY |
| M1 | M570_JTAG_EN | 3.3-V | Fa'ailoga maualalo e fa'amalo ai le USB-Blaster II |
| P10 | MAX5_BEN0 | 2.5-V | FSM pasi MAX V byte mafai 0 |
| R11 | MAX5_BEN1 | 2.5-V | FSM pasi MAX V byte mafai 1 |
| T12 | MAX5_BEN2 | 2.5-V | FSM pasi MAX V byte mafai 2 |
| N11 | MAX5_BEN3 | 2.5-V | FSM pasi MAX V byte mafai 3 |
| T11 | MAX5_CLK | 2.5-V | FSM pasi MAX V uati |
| R10 | MAX5_CSN | 2.5-V | FSM pasi MAX V chip filifili |
| M10 | MAX5_OEN | 2.5-V | FSM pasi MAX V fa'aagaoioiga |
| N10 | MAX5_WEN | 2.5-V | FSM pasi MAX V tusi mafai |
| E11 | MAX_CONF_DONEN | 2.5-V | Fa'apipi'i USB-Blaster II fa'atulagaina fa'atino LED |
| A4 | MAX_ERROR | 2.5-V | FPGA fetuutuunaiga sese LED |
| A6 | MAX_LOAD | 2.5-V | FPGA fetuutuunai LED galue |
| M9 | MAX_RESETN | 2.5-V | MAX V toe setiina le faamau |
| B7 | OVERTEMP | 2.5-V | E mafai e le ili mata'ituina le vevela |
| D12 | PGM_CONFIG | 2.5-V | U'u le ata fa'amalama e iloa mai e PGM LEDs |
| B14 | PGM_LED0 | 2.5-V | Flash memory PGM filifili faailoga 0 |
| C13 | PGM_LED1 | 2.5-V | Flash memory PGM filifili faailoga 1 |
| B16 | PGM_LED2 | 2.5-V | Flash memory PGM filifili faailoga 2 |
| B13 | PGM_SEL | 2.5-V | Su'e le fa'asologa o le PGM_LED[2:0] LED |
| H4 | PSAS_CSn | 3.3-V | AS fetuutuunaiga chip filifili |
| G1 | PSAS_DCLK | 3.3-V | AS fetuutuunaiga uati |
| G4 | PSAS_CONF_FAIA | 3.3-V | AS fa'atulagaina ua mae'a |
| H2 | PSAS_CONFIGn | 3.3-V | AS fa'atulagaina fa'agaoioi |
| G5 | PSAS_DATA1 | 3.3-V | AS fa'amaumauga fa'atulagaina |
| H3 | PSAS_DATA0_ASD0 | 3.3-V | AS fa'amaumauga fa'atulagaina |
| J1 | PSAS_CEn | 3.3-V | AS fetuutuunaiga chip mafai |
| R12 | SECURITY_MODE | 2.5-V | DIP ki mo le USB-Blaster II fa'apipi'i e tu'uina atu le fa'atonuga FACTORY i luga |
| E7 | SENSE_CS0N | 2.5-V | Pule mataitu pusi filifili |
| A5 | SENSE_SCK | 2.5-V | Uati mataitu SPI mana |
| D7 | SENSE_SDI | 2.5-V | Mataitu eletise SPI faʻamaumauga i totonu |
| B6 | SENSE_SDO | 2.5-V | Malosiaga mata'itu fa'amatalaga SPI |
Fa'atonuga FPGA
O le vaega lea o lo'o fa'amatalaina ai le FPGA, flash memory, ma le MAX V CPLD 5M2210 System Controller auala fa'apolokalameina o masini e lagolagoina e le Afa VE FPGA atina'e.
E lagolagoina e le Cyclone VE FPGA development board auala fa'atulagaina nei:
- Embedded USB-Blaster II o le auala le lelei mo le faʻatulagaina o le FPGA e faʻaaoga ai le Quartus II Programmer i le J.TAG faiga fa'atasi ma le uaea USB ua tu'uina atu.
- Fa'asao fa'amanatuga mo le fa'atulagaina o le FPGA i le fa'aogaina o ata o lo'o teuina mai le flash memory i luga o so'o se mana-i luga po'o le oomiina o le fa'amau fa'apipi'i o le polokalame (S1).
- USB-Blaster fafo mo le faʻatulagaina o le FPGA e faʻaaoga ai se USB-Blaster fafo e fesoʻotaʻi i le JTAG ulutala filifili (J4).
- EPCQ masini mo fa'asologa fa'asologa po'o le quad-serial FPGA fa'atulagaina e lagolagoina AS x1 po'o le AS x4 fa'atulagaina polokalame.
Polokalama FPGA i luga ole Embedded USB-Blaster II
O lenei metotia faʻatulagaina e faʻaogaina ai le USB type-B connector (J10), se USB 2.0 PHY device (U18), ma le Altera MAX II CPLD EPM570GF100I5N (U16) e faʻatagaina ai le faʻaogaina o le FPGA e faʻaaoga ai le USB cable. O lenei uaea USB e fesoʻotaʻi saʻo i le va o le USB type-B connector i luga o le laupapa ma le USB port o se PC o loʻo faʻaogaina le polokalama Quartus II.
O le USB-Blaster II faʻapipiʻiina i le MAX II CPLD EPM570GF100I5N e masani ona faʻatautaia le JTAG filifili.
O le ata 2–3 o loʻo faʻaalia ai le JTAG filifili.
O le JTAG filifili filifili DIP ki (SW2) pulea le osooso o loo faaalia i le Ata 2–3.
Ina ia faʻafesoʻotaʻi se masini poʻo se atinaʻe i le filifili, o la latou ki faʻatatau e tatau ona i ai i le tulaga OFF. Fa'asolo uma ki i le tulaga ON e na'o le FPGA i le filifili.
Ole MAX V CPLD 5M2210 System Controller e tatau ona iai ile JTAG filifili e faʻaoga ai nisi o fesoʻotaʻiga GUI.
Siata 2–5 o lo'o lisiina ai igoa fa'ailoga o le USB 2.0 PHY ma latou numera pine o le Afa VE FPGA.
Laulau 2–5. USB 2.0 PHY Schematic Signal Igoa ma Galuega (Vaega 1 o le 2)
| Fa'asinomaga a le Komiti Fa'atonu (U18) | Fuafuaga Fa'ailoga Igoa | Afa VE Numera Pin FPGA | I/O Tulaga | Fa'amatalaga |
| C1 | 24M_XTALIN | — | 3.3-V | Oscillator tioata |
| C2 | 24M_XTALOUT | — | 3.3-V | Fa'atosina oscillator tioata |
| E1 | FX2_D_N | — | 3.3-V | USB 2.0 PHY fa'amaumauga |
| E2 | FX2_D_P | — | 3.3-V | USB 2.0 PHY fa'amaumauga |
| H7 | FX2_FLAGA | — | 3.3-V | Tulaga o galuega a le FIFO pologa |
Laulau 2–5. USB 2.0 PHY Schematic Signal Igoa ma Galuega (Vaega 2 o le 2)
| Fa'asinomaga a le Komiti Fa'atonu (U18) | Fuafuaga Fa'ailoga Igoa | Afa VE Numera Pin FPGA | I/O Tulaga | Fa'amatalaga |
| G7 | FX2_FLAGB | — | 3.3-V | Tulaga o galuega a le FIFO pologa |
| H8 | FX2_FLAGC | — | 3.3-V | Tulaga o galuega a le FIFO pologa |
| G6 | FX2_PA1 | — | 3.3-V | USB 2.0 PHY uafu A fa'aoga |
| F8 | FX2_PA2 | — | 3.3-V | USB 2.0 PHY uafu A fa'aoga |
| F7 | FX2_PA3 | — | 3.3-V | USB 2.0 PHY uafu A fa'aoga |
| F6 | FX2_PA4 | — | 3.3-V | USB 2.0 PHY uafu A fa'aoga |
| C8 | FX2_PA5 | — | 3.3-V | USB 2.0 PHY uafu A fa'aoga |
| C7 | FX2_PA6 | — | 3.3-V | USB 2.0 PHY uafu A fa'aoga |
| C6 | FX2_PA7 | — | 3.3-V | USB 2.0 PHY uafu A fa'aoga |
| H3 | FX2_PB0 | — | 3.3-V | USB 2.0 PHY uafu B fa'aoga |
| F4 | FX2_PB1 | — | 3.3-V | USB 2.0 PHY uafu B fa'aoga |
| H4 | FX2_PB2 | — | 3.3-V | USB 2.0 PHY uafu B fa'aoga |
| G4 | FX2_PB3 | — | 3.3-V | USB 2.0 PHY uafu B fa'aoga |
| H5 | FX2_PB4 | — | 3.3-V | USB 2.0 PHY uafu B fa'aoga |
| G5 | FX2_PB5 | — | 3.3-V | USB 2.0 PHY uafu B fa'aoga |
| F5 | FX2_PB6 | — | 3.3-V | USB 2.0 PHY uafu B fa'aoga |
| H6 | FX2_PB7 | — | 3.3-V | USB 2.0 PHY uafu B fa'aoga |
| A8 | FX2_PD0 | — | 3.3-V | USB 2.0 PHY uafu D fa'aoga |
| A7 | FX2_PD1 | — | 3.3-V | USB 2.0 PHY uafu D fa'aoga |
| B6 | FX2_PD2 | — | 3.3-V | USB 2.0 PHY uafu D fa'aoga |
| A6 | FX2_PD3 | — | 3.3-V | USB 2.0 PHY uafu D fa'aoga |
| B3 | FX2_PD4 | — | 3.3-V | USB 2.0 PHY uafu D fa'aoga |
| A3 | FX2_PD5 | — | 3.3-V | USB 2.0 PHY uafu D fa'aoga |
| C3 | FX2_PD6 | — | 3.3-V | USB 2.0 PHY uafu D fa'aoga |
| A2 | FX2_PD7 | — | 3.3-V | USB 2.0 PHY uafu D fa'aoga |
| B8 | FX2_RESETN | V21 | 3.3-V | Fa'amauina USB-Blaster toe setiina malosi |
| F3 | FX2_SCL | — | 3.3-V | USB 2.0 PHY uati faasologa |
| G3 | FX2_SDA | — | 3.3-V | USB 2.0 PHY fa'amaumauga fa'asologa |
| A1 | FX2_SLRDN | — | 3.3-V | Faitau strobe mo pologa FIFO |
| B1 | FX2_SLWRN | — | 3.3-V | Tusi strobe mo pologa FIFO |
| B7 | FX2_WAKEUP | — | 3.3-V | Fa'ailoga fafagu USB 2.0 PHY |
| G2 | USB_CLK | AA23 | 3.3-V | USB 2.0 PHY 48-MHz fa'aoga uati |
Polokalama FPGA mai Flash Memory
E mafai ona fa'apolokalameina le flash memory e ala i auala eseese. O le auala fa'aletonu o le fa'aogaina lea o le falegaosimea—Board Update Portal. O lenei mamanu o se faʻapipiʻi webserver, lea e tautuaina le Portal Update Portal web itulau. O le web itulau e mafai ai e oe ona filifili ni mamanu fou FPGA e aofia ai meafaigaluega, polokalama, poʻo mea uma e lua i totonu ole S-Faʻamaumauga faʻapitoa. File (.flash) ma tusi le mamanu i le itulau o meafaigaluega a le tagata e faaaogāina (itulau 1) o le flash memory i luga o le upega tafailagi.
O le auala lona lua o le faʻaaogaina lea o le faʻapipiʻi faʻapipiʻi parallel loader (PFL) mamanu o loʻo aofia i totonu o le pusa atinaʻe. O lo'o fa'atinoina e le komiti fa'atupuina le Altera PFL megafunction mo polokalame e manatua ai le flash. O le PFL megafunction o se poloka o manatu ua faʻapipiʻiina i totonu ole Altera programmable logic device (FPGA poʻo CPLD). O le PFL o loʻo galue o se aoga mo le tusitusi i se masini manatua flash talafeagai. O lenei mamanu na muai fausia o loʻo i ai le PFL megafunction e mafai ai ona e tusia le itulau 0, itulau 1, poʻo isi vaega o le mafaufau moli i luga o le USB interface e faʻaaoga ai le polokalama Quartus II. O lenei metotia e faʻaaogaina e toe faʻafoʻi ai le laupapa atinaʻe i ona tulaga faʻaletonu fale gaosimea.
O isi auala e fa'apolokalame ai le flash memory e mafai fo'i ona fa'aoga, e aofia ai le Nios® II processor.
Mo nisi faʻamatalaga i le Nios II processor, vaʻai ile Nios II Processor itulau ole Altera webnofoaga.
I so'o se eletise po'o le oomiina o le fa'apolokalame fa'apipi'i fa'amau fa'amau, PGM_CONFIG (S1), o le MAX V CPLD 5M2210 System Controller's PFL e fa'aogaina le FPGA mai le flash memory. O le PFL megafunction e faitau 16-bit faʻamaumauga mai le flash memory ma faʻaliliuina i le faʻataʻitaʻiga faʻatasi vave (FPP). O lenei 16-bit faʻamaumauga ona tusi lea i pine faʻapipiʻi tuʻufaʻatasia i le FPGA i le taimi o faʻatulagaga.
O le oomiina o le PGM_CONFIG push button (S1) e utaina ai le FPGA ma se itulau o meafaigaluega e faʻatatau i le PGM_LED[2:0] (D25, D26, D27) e faʻamalamalamaina. Laulau 2-6 o lo'o lisiina ai le mamanu e utaina pe a e oomiina le PGM_CONFIG fa'amau.
Laulau 2–6. PGM_LED Fa'atonu (1)
| PGM_LED0 (D25) | PGM_LED1 (D26) | PGM_LED2 (D27) | Fuafuaga |
| ON | TOTO | TOTO | Meafaigaluega falegaosimea |
| TOTO | ON | TOTO | Fa'aoga meafaigaluega 1 |
| TOTO | TOTO | ON | Fa'aoga meafaigaluega 2 |
Ata 2–4 o lo'o fa'aalia ai le fa'atulagaina o le PFL.
Mo nisi fa'amatalaga i mataupu nei, va'ai i pepa ta'itasi:
- Board Update Portal, PFL design, and flash memory map storage, tagai ile Cyclone VE FPGA Development Kit User Guide.
- PFL megafunction, tagai ile Parallel Flash Loader Megafunction User Guide.
Polokalama FPGA i luga ole USB-Blaster fafo
O le JTAG O le ulutala filifili e maua ai se isi auala mo le faʻatulagaina o le FPGA e faʻaaoga ai se masini USB-Blaster fafo ma le Quartus II Programmer o loʻo faʻaogaina i luga o se PC. Ina ia taofia finauga i le va o le JTAG matai, o le USB-Blaster fa'apipi'i e otometi lava ona fa'aletonu pe a e fa'afeso'ota'i se USB-Blaster fafo i le J.TAG filifili e ala i le JTAG ulutala filifili.
FPGA Polokalama fa'aaoga EPCQ
O le masini ECPQ taugofie ma le manatua e le faʻafefeteina o loʻo faʻaalia ai se faʻaoga faigofie ono-pin ma se faʻailoga laʻititi. O le ECPQ e lagolagoina AS x1 ma x4 auala. Ona o le faaletonu, o lenei laupapa o loʻo i ai se faʻatulagaina o fuafuaga faʻatulagaina FPP. Ina ia mafai ona seti le faʻatulagaga faʻatulagaina i le AS mode, e manaʻomia le toe faʻaleleia o le tetee. Fa'atulaga le MSEL fa'aoga le MSEL DIP switch (SW1) e sui ai le polokalame fa'atulagaina.
Ata 2–5 o lo'o fa'aalia ai le feso'ota'iga i le va o le EPCQ ma le Afa VE FPGA.
Ata 2–5. EPCQ Configuration
Tulaga Elemene
O le laupapa atinaʻe e aofia ai tulaga LEDs. O lenei vaega o loʻo faʻamatalaina elemene tulaga.
Lisi 2–7 o lo'o lisi ai fa'amatalaga laupapa fa'a LED, igoa, ma fa'amatalaga fa'atino.
Laulau 2–7. LED Fa'apitoa a le Komiti Fa'atonu (Vaega 1 o le 2)
| Komiti Fa'atonu Fa'asinomaga | Fuafuaga Fa'ailoga Igoa | I/O Tulaga | Fa'amatalaga |
| D35 | Malosiaga | 5.0-V | LED lanumoana. E fa'amalamalama pe a fa'agaoioi le malosi ole 5.0 V. |
| D19 | MAX_CONF_DONEn | 2.5-V | LED lanu meamata. E fa'amalamalama pe a fa'atulaga lelei le FPGA. Fa'atonu e le MAX V CPLD 5M2210 System Controller. |
|
D17 |
MAX_ERROR |
2.5-V |
LED mumu. E susulu pe a le mafai e le MAX V CPLD 5M2210 System Controller ona faʻapipiʻi le FPGA. Fa'atonu e le MAX V CPLD 5M2210 System Controller. |
|
D18 |
MAX_LOAD |
2.5-V |
LED lanu meamata. E fa'amalamalamaina pe a fa'agaoioia e le MAX V CPLD 5M2210 System Controller le FPGA. Fa'atonu e le MAX V CPLD 5M2210 System Controller. |
| D25
O26 D27 |
PGM_LED[0]
PGM_LED[1] PGM_LED[2] |
2.5-V |
LED lanu meamata. E fa'amalamalama e fa'ailoa mai ai po'o fea itulau o meafaigaluega e utaina mai le flash memory pe a e oomiina le PGM_SEL pa'u. |
Laulau 2–7. LED Fa'apitoa a le Komiti Fa'atonu (Vaega 2 o le 2)
| Komiti Fa'atonu Fa'asinomaga | Fuafuaga Fa'ailoga Igoa | I/O Tulaga | Fa'amatalaga |
| D11, D12
D13, D14 |
JTAG_RX, JTAG_TX
SC_RX, SC_TX |
2.5-V | LED lanu meamata. Faʻamalamalama e faʻaalia ai le USB-Blaster II maua ma faʻasalalau gaioiga. |
| D1 | ENETA_LED_TX | 2.5-V | LED lanu meamata. E fa'amalamalama e fa'ailoa ai le Ethernet PHY fe'avea'i gaioiga. Fa'aola e le Marvell 88E1111 PHY. |
| D2 | ENETA_LED_RX | 2.5-V | LED lanu meamata. E fa'amalamalama e fa'ailoa ai le Ethernet PHY e maua le gaioiga. Fa'aola e le Marvell 88E1111 PHY. |
| D5 | ENETA_LED_LINK10 | 2.5-V | LED lanu meamata. E fa'amalamalama e fa'ailoa ai le feso'ota'iga Ethernet i le saoasaoa o feso'ota'iga 10 Mbps. Fa'aola e le Marvell 88E1111 PHY. |
| D4 | ENETA_LED_LINK100 | 2.5-V | LED lanu meamata. E fa'amalamalama e fa'ailoa ai le feso'ota'iga Ethernet i le saoasaoa o feso'ota'iga 100 Mbps. Fa'aola e le Marvell 88E1111 PHY. |
| D3 | ENETA_LED_LINK1000 | 2.5-V | LED lanu meamata. E fa'amalamalama e fa'ailoa ai le feso'ota'iga Ethernet i le saoasaoa o feso'ota'iga 1000 Mbps. Fa'aola e le Marvell 88E1111 PHY. |
| D19 | ENETB_LED_TX | 2.5-V | LED lanu meamata. E fa'amalamalama e fa'ailoa ai le Ethernet PHY B fa'aliliuina le gaioiga. Fa'aola e le Marvell 88E1111 PHY. |
| D22 | ENETB_LED_RX | 2.5-V | LED lanu meamata. E fa'amalamalama e fa'ailoa ai le Ethernet PHY B maua gaioioiga. Fa'aola e le Marvell 88E1111 PHY. |
| D24 | ENETB_LED_LINK10 | 2.5-V | LED lanu meamata. E fa'amalamalama e fa'ailoa ai le Ethernet B o lo'o feso'ota'i ile 10 Mbps saoasaoa feso'ota'iga. Fa'aola e le Marvell 88E1111 PHY. |
| D20 | ENETB_LED_LINK100 | 2.5-V | LED lanu meamata. E fa'amalamalama e fa'ailoa ai le Ethernet B o lo'o feso'ota'i ile 100 Mbps saoasaoa feso'ota'iga. Fa'aola e le Marvell 88E1111 PHY. |
| D21 | ENETB_LED_LINK1000 | 2.5-V | LED lanu meamata. E fa'amalamalama e fa'ailoa ai le Ethernet B o lo'o feso'ota'i ile 1000 Mbps saoasaoa feso'ota'iga. Fa'aola e le Marvell 88E1111 PHY. |
| D15, D16 | USB_UART_TX_TOGGLE, USB_UART_RX_TOGGLE | 2.5-V | LED lanu meamata. E fa'amalamalama e fa'ailoa mai ai le USB_UART e maua ma fa'asalalau gaioiga. |
| D23, D24 | UART_RXD_LED, UART_TXD_LED | 2.5-V | LED lanu meamata. E fa'amalamalama e fa'ailoa ai le mauaina e le UART ma le fa'asalalauina o gaioiga. |
|
D3 |
HSMA_PRSNTn |
3.3-V |
LED lanu meamata. E moli pe a iai se laupapa po'o se uaea fa'apipi'i i totonu o le uafu o le HSMC ina ia fa'amauina ai le pine 160. Fa'atonu e le kata fa'aopoopo. |
Seti Elemene
O le laupapa atina'e e aofia ai ituaiga eseese o elemene seti. O lenei vaega o loʻo faʻamatalaina elemene seti nei:
- Fa'atonu a le komiti sui DIP
- JTAG seti DIP ki
- PPU toe setiina oomi faamau
- MAX V toe setiina le faamau
- Fa'amau fa'atonu polokalame
- Polokalama filifili kiliki faamau
Mo nisi fa'amatalaga e uiga i le fa'aogaina o suiga ole DIP, tagai ile Cyclone VE FPGA Development Kit User Guide.
Fa'atonu Fa'atonu DIP Suiga
O le fa'atulagaina o le laupapa DIP switch (SW4) e fa'atonutonu ai vaega eseese o le laupapa ma le MAX V CPLD 5M2210 System Controller logic design. Lisi 2–8 o lo'o lisiina ai fa'atonuga ma fa'amatalaga.
Laulau 2–8. Fa'atonu Fa'atonu Pulea Suiga DIP
| Suiga | Fuafuaga Fa'ailoga Igoa | Fa'amatalaga |
| 1 |
CLK_SEL |
ON : Filifili polokalamemable oscillator uati
TOTO: Filifili le uati ulufale SMA |
| 2 |
CLK_ENABLE |
ON : Ta'e le oscillator i luga o le laupapa
OFF : Fa'aagaoi le oscillator i luga ole laupapa |
| 3 |
FACTORY_LOAD |
ON: U'u le mamanu a le tagata fa'aoga mai le moli i luga o le eletise
OFF: U'u le mamanu falegaosimea mai le moli i luga o le eletise |
|
4 |
SECURITY_MODE |
ON: Embedded USB-Blaster II auina atu FACTORY command i le paoa.
OFF: Embedded USB-Blaster II e le auina atu le FACTORY command i le paoa. |
JTAG Suiga DIP Pulea filifili
O le JTAG filifili filifili DIP ki (SW2) pe aveese pe aofia ai masini i le JTAG filifili. O le Afa VE FPGA o loʻo i ai pea i le JTAG filifili. Laulau 2-9 o lo'o lisiina ai le fa'atonuga o ki ma ona fa'amatalaga.
Laulau 2–9. JTAG Suiga DIP Pulea filifili
| Suiga | Fuafuaga Fa'ailoga Igoa | Fa'amatalaga |
| 1 |
5M2210_JTAG_EN |
ON: Ta'alo MAX V CPLD 5M2210 Pule Fa'atonu
MATE: MAX V CPLD 5M2210 Pule Fa'atonu i totonu filifili |
| 2 |
HSMC_JTAG_EN |
ON : Ta'alo le uafu HSMC
OFF: HSMC uafu i-fifili |
| 3 |
FAN_FORCE_ON |
ON : Fa'aaga ili
TOTO: Ta'e le ili |
| 4 | FAAVAE | Fa'apolopolo |
CPU Toe Seti Push Button
O le CPU reset push button, CPU_RESETn (S4), o se fa'aoga i le Cyclone VE FPGA DEV_CLRn pine ma o se I/O tatala-vai mai le MAX V CPLD System Controller. O lenei fa'amau fa'amau o le seti fa'aletonu mo le FPGA ma le CPLD logic. O le MAX V CPLD 5M2210 System Controller na te fa'auluina fo'i lenei fa'amau fa'amau i le taimi o le toe fa'aleleia o le mana (POR).
MAX V Toe Seti Push Button
O le MAX V reset push button, MAX_RESETn (S3), o se fa'aoga i le MAX V CPLD 5M2210 System Controller. O lenei fa'amau fa'amau o le seti fa'aletonu mo le CPLD logic.
Fa'atonu Polokalama Push Button
O le faʻamau faʻapipiʻiina o le polokalame, PGM_CONFIG (S1), o se faʻaoga i le MAX V CPLD 5M2210 System Controller. O lenei fa'aoga e fa'amalosia ai le toe fa'afouina o le FPGA mai le flash memory. Ole nofoaga ile flash memory e fa'avae ile PGM_LED[2:0], lea e pulea e le polokalame filifili fa'amau fa'amau, PGM_SEL. Fa'atonuga fa'aoga e aofia ai le PGM_LED0, PGM_LED1, po'o le PGM_LED2 i luga o itulau e tolu i le flash memory fa'aagaga mo mamanu FPGA.
Polokalama Filifili Push Button
O le polokalame filifili fa'amau fa'amau, PGM_SEL (S2), o se fa'aoga i le MAX V CPLD 5M2210 System Controller. O le fa'amau fa'amau e fa'asolo ai le fa'asologa o le PGM_LED[2:0] e filifili po'o fea nofoaga i le flash memory e fa'aoga e fa'atulaga ai le FPGA. Va'ai ile Laulau 2–6 mo le PGM_LED[2:0] fa'auiga fa'asologa.
Uati Li'o
O lenei vaega o lo'o fa'amatala ai mea e fa'aoga ma mea e fa'atino ai le uati.
Oscillators i luga ole laupapa
O le laupapa atinaʻe e aofia ai oscillators ma le tele o le 50-MHz, 100-MHz, ma se oscillator e mafai ona faʻapipiʻiina.
Ata 2–6 o lo'o fa'aalia ai alaleo fa'aletonu o uati uma i fafo o lo'o alu i le laupapa atina'e o le Afa VE FPGA.
Ata 2–6. Uati Komiti Atina'e o le Afa VE FPGA
Laulau 2-10 lisi oscillators, lona tulaga I/O, ma voltage mana'omia mo le komiti atina'e.
Laulau 2–10. Oscillators i luga ole laupapa
| Punavai | Fuafuaga Fa'ailoga Igoa | Fa'atele | I/O Tulaga | Afa VE Numera Pin FPGA | Fa'atatauga |
| U4 | CLKIN_50_FPGA_TOP | 50.000 MHz | Nofofua-toʻatasi | L14 | pito pito i luga ma taumatau |
| CLKIN_50_FPGA_RIGHT | P22 | ||||
| X3 | CLK_CONFIG | 100.000 MHz | 2.5V CMOS | — | Fa'atonuga vave FPGA |
|
X1 ma le U3 (pa'u) |
DIFF_CLKIN_TOP_125_P |
125.000 MHz |
LVDS |
L15 |
pito pito i luga ma lalo |
| DIFF_CLKIN_TOP_125_N | K15 | ||||
| DIFF_CLKIN_BOT_125_P | AB17 | ||||
| DIFF_CLKIN_BOT_125_N | AB18 |
Ulufale Uati Ulufale/Auina
O lo'o iai uati fa'aulufalega ma uati fa'atino e mafai ona fa'aoso i luga o le laupapa. E mafai ona fa'apolokalame le uati o galuega i tulaga eseese ma tulaga I/O e tusa ai ma fa'amatalaga a le masini FPGA.
O le laulau 2–11 o lo'o lisiina ai mea e fa'aoga ai uati mo le laupapa atina'e.
Laulau 2–11. Ulufale Uati Ulufale
|
Punavai |
Fa'ailoga Fa'ailoga Igoa |
I/O Tulaga |
Afā V E FPGA Pin
Numera |
Fa'amatalaga |
| SMA | CLKIN_SMA_P | LVDS | — | Ulufale i le LVDS fan-out buffer. |
| CLKIN_SMA_N | LVDS | — | ||
| Samtec HSMC | HSMA_CLK_IN0 | 2.5-V | AB16 | Fa'aoga tasi fa'ai'u mai le uaea HSMC fa'apipi'i po'o le laupapa. |
| Samtec HSMC | HSMA_CLK_IN_P1 | LVDS/2.5-V | AB14 | LVDS fa'aoga mai le uaea HSMC fa'apipi'i po'o le laupapa. E mafai foi ona lagolagoina 2x LVTTL mea e fai. |
| HSMA_CLK_IN_N1 | LVDS/LVTTL | AC14 | ||
| Samtec HSMC | HSMA_CLK_IN_P2 | LVDS/LVTTL | Y15 | LVDS fa'aoga mai le uaea HSMC fa'apipi'i po'o le laupapa. E mafai foi ona lagolagoina 2x LVTTL mea e fai. |
| HSMA_CLK_IN_N2 | LVDS/LVTTL | AA15 |
Laulau 2–12 o lo'o lisiina ai galuega faatino o le uati mo le laupapa atina'e.
Laulau 2–12. Outputs Uati i fafo-Board
|
Punavai |
Fa'ailoga Fa'ailoga Igoa |
I/O Tulaga |
Afā V E FPGA Pin
Numera |
Fa'amatalaga |
| Samtec HSMC | HSMA_CLK_OUT0 | 2.5V CMOS | AJ14 | FPGA CMOS gaioiga (po'o le GPIO) |
| Samtec HSMC | HSMA_CLK_OUT_P1 | LVDS/2.5V CMOS | AE22 | LVDS gaosiga. E mafai foi ona lagolagoina 2x CMOS gaioiga. |
| HSMA_CLK_OUT_N1 | LVDS/2.5V CMOS | AF23 | ||
| Samtec HSMC | HSMA_CLK_OUT_P2 | LVDS/2.5V CMOS | AG23 | LVDS gaosiga. E mafai foi ona lagolagoina 2x CMOS gaioiga. |
| HSMA_CLK_OUT_N2 | LVDS/2.5V CMOS | AH22 | ||
| SMA | CLKOUT_SMA | 2.5V CMOS | F9 | FPGA CMOS gaioiga (po'o le GPIO) |
Fa'aoga Lautele Fa'aoga Fa'aoga/Gofuafua
O lenei vaega o loʻo faʻamatalaina ai le faʻaoga I/O faʻaoga i le FPGA, e aofia ai faʻamau faʻamau, sui DIP, LED, ma amio LCD.
Push Buttons e Fa'ailoaina e le Tagata Fa'aaoga
O le laupapa atinaʻe e aofia ai faʻamau faʻaogaina e tolu e faʻaogaina e le tagata faʻaoga. Mo faamatalaga i le faiga ma le toe setiina o faamau oomi saogalemu, tagai i le “Setup Elements” i le itulau 2–16. O fa'asinoga a le Komiti Fa'atonu S5, S6, S7, ma le S8 o fa'amau fa'atonu mo le fa'atonutonuina o mamanu FPGA o lo'o uta i totonu o le masini FPGA Cyclone VE. A e oomi ma taofi i lalo le ki, e seti le pine o le masini i le logic 0; pe a e tatalaina le ki, ua setiina le pine o le masini i le logic 1. E leai ni galuega faʻapitoa a le laupapa mo nei faʻaoga masani faʻaoga faʻaoga.
Lisi 2–13 o lo'o lisiina ai igoa fa'ailo fa'aigoa fa'aigoa fa'aoga e fa'auigaina ma latou numera pine o le Afa VE FPGA.
Laulau 2–13. Igoa Fa'ailoga Fa'ailoga ma Galuega Fa'atino e Fa'asinoina e le Tagata Fa'aaoga
| Komiti Fa'atonu Fa'asinomaga | Fuafuaga Fa'ailoga Igoa | Afa VE FPGA Pin Numera | I/O Tulaga |
| S5 | USER_PB0 | AB12 | 2.5-V |
| S6 | USER_PB1 | AB13 | 2.5-V |
| S7 | USER_PB2 | AF13 | 2.5-V |
| S8 | USER_PB3 | AG12 | 2.5-V |
Suiga DIP Fa'a-Fa'aoga
O le fa'asinoga a le Komiti Fa'atonu SW3 o le fa-pin DIP ki. O lenei ki e faʻamalamalamaina e le tagata faʻaoga ma maua ai le faʻaogaina o le FPGA faʻaopoopo. A o'o le ki i le tulaga OFF, ua filifilia se manatu 1. A o'o le ki i le tulaga ON, ua filifilia se manatu 0. E leai ni galuega fa'apitoa mo lenei ki.
Siata 2–14 o lo'o lisi ai igoa fa'ailoga ole DIP fa'auiga e fa'aogaina e le tagata fa'aoga ma latou numera pine o le Afa VE FPGA.
Laulau 2–14. Igoa Fa'ailoga ma Galuega Fa'atino a le DIP Fa'aigoaina e le Fa'aoga
| Komiti Fa'atonu Fa'asinomaga | Fuafuaga Fa'ailoga Igoa | Afa VE FPGA Pin Numera | I/O Tulaga |
| S5 | USER_PB0 | AB12 | 2.5-V |
| S6 | USER_PB1 | AB13 | 2.5-V |
| S7 | USER_PB2 | AF13 | 2.5-V |
| S8 | USER_PB3 | AG12 | 2.5-V |
LED fa'a-Fa'aoga
O le komiti atina'e e aofia ai fa'amalama lautele ma le HSMC fa'aogaina e tagata fa'aoga. O lenei vaega o loʻo faʻamatalaina uma LED faʻamalamalamaina e tagata faʻaoga. Mo faʻamatalaga i luga o le laupapa faʻapitoa poʻo le tulaga o LED, tagai i le “Elemene Tulaga” i le itulau 2–15.
LED lautele
Fa'amatalaga a le Komiti Fa'atonu D28 e o'o i le D31 e fa fa'auiga fa'aoga LED. O le tulaga ma fa'ailoga fa'apipi'i o lo'o fa'ao'o atu ile LED mai mamanu na utaina ile Afa VE FPGA. O le aveina o se manatu 0 i luga o le I/O uafu e liliu ai le LED a'o ave se manatu 1 e tape le LED. E leai ni galuega fa'apitoa a le laupapa mo nei LED.
Siata 2–15 o lo'o lisiina ai igoa fa'ailo fa'ailoga masani a le LED ma latou numera pine o le Afa VE FPGA.
Laulau 2–15. Igoa Fa'ailoga Fa'ailoga o le LED lautele ma Galuega
| Komiti Fa'atonu Fa'asinomaga | Fuafuaga Igoa Faailoga | Afa VE FPGA Numera Pin | I/O Tulaga |
| D28 | USER_LED0 | AK3 | 2.5-V |
| D29 | USER_LED1 | AJ4 | 2.5-V |
| D30 | USER_LED2 | AJ5 | 2.5-V |
| D31 | USER_LED3 | AK6 | 2.5-V |
HSMC LEDs
O fa'amatalaga a le Komiti D20 ma le D21 o fa'ailo mo le uafu HSMC. E leai ni galuega fa'apitoa mo le HSMC LED. O LED ua fa'aigoaina TX ma RX, ma ua fa'amoemoe e fa'aali atu fa'amatalaga fa'asolo atu i ma mai i kata teine feso'ota'i. O LED o lo'o fa'auluina e le masini FPGA Cyclone VE.
Siata 2–16 o lo'o lisiina ai igoa fa'ailoga fa'ailoga a le HSMC LED ma latou numera pine o le Afa VE FPGA.
Laulau 2–16. HSMC LED Schematic Signal Igoa ma Galuega
| Komiti Fa'atonu Fa'asinomaga | Fuafuaga Igoa Faailoga | Afa VE FPGA Pin Numera | I/O Tulaga |
| D1 | HSMC_RX_LED | AH12 | 2.5-V |
| D2 | HSMC_TX_LED | AH11 | 2.5-V |
amio LCD
O le laupapa atina'e e aofia ai le 14-pin 0.1″ pitch lua-laina ulutala e fa'afeso'ota'i i se laina 2 × 16 amio Lumex amio LCD. O le amio LCD ei ai se pusa 14-pin e fa'apipi'i sa'o i le ulutala 14-pin a le laupapa, ina ia faigofie ona aveese mo le avanoa i vaega i lalo o le fa'aaliga. E mafai foʻi ona e faʻaogaina le ulutala mo le faʻapipiʻiina poʻo isi faʻamoemoega.
O le Siata 2–17 o lo'o aoteleina ai galuega fa'akomepiuta LCD. O igoa fa'ailo ma fa'atonuga e feso'ota'i ma le masini FPGA Cyclone VE.
Laulau 2–17. Uiga LCD Pin Tofiga, Fa'ailoga Igoa Fa'ailoga, ma Galuega
| Komiti Fa'atonu Fa'amatalaga (J14) | Igoa Fa'ailoga Fa'ailoga | Afa VE FPGA Numera Pin | I/O Tulaga | Fa'amatalaga |
| 7 | LCD_DATA0 | AJ7 | 2.5-V | pasi fa'amatalaga LCD |
| 8 | LCD_DATA1 | AK7 | 2.5-V | pasi fa'amatalaga LCD |
| 9 | LCD_DATA2 | AJ8 | 2.5-V | pasi fa'amatalaga LCD |
| 10 | LCD_DATA3 | AK8 | 2.5-V | pasi fa'amatalaga LCD |
| 11 | LCD_DATA4 | AF9 | 2.5-V | pasi fa'amatalaga LCD |
| 12 | LCD_DATA5 | AG9 | 2.5-V | pasi fa'amatalaga LCD |
| 13 | LCD_DATA6 | AH9 | 2.5-V | pasi fa'amatalaga LCD |
| 14 | LCD_DATA7 | AJ9 | 2.5-V | pasi fa'amatalaga LCD |
Laulau 2–17. Uiga LCD Pin Tofiga, Fa'ailoga Igoa Fa'ailoga, ma Galuega
| Komiti Fa'atonu Fa'amatalaga (J14) | Igoa Fa'ailoga Fa'ailoga | Afa VE FPGA Numera Pin | I/O Tulaga | Fa'amatalaga |
| 4 | LCD_D_Cn | AK11 | 2.5-V | LCD faʻamatalaga poʻo le poloaiga filifili |
| 5 | LCD_WEn | AK10 | 2.5-V | LCD tusitusi mafai |
| 6 | LCD_CSn | AJ12 | 2.5-V | Filifili pu'e LCD |
O le laulau 2–18 o lo'o lisiina ai fa'amatalaga o pine LCD, ma o se vaega mai le pepa fa'amaumauga a le Lumex.
Laulau 2–18. LCD Pin Fa'amatalaga ma Galuega
| Pin Numera | Faailoga | Tulaga | Galuega | |
| 1 | VDD | — |
Paoa sapalai |
5 V |
| 2 | VSS | — | GND (0 V) | |
| 3 | V0 | — | Mo le ta'avale LCD | |
|
4 |
RS |
H/L |
Resitala filifili faailo H: Fa'amatalaga fa'amatalaga
L: Fa'atonuga |
|
| 5 | R/W | H/L | H: Fa'amatalaga faitau (module i MPU)
L: Tusi fa'amaumauga (MPU i le module) |
|
| 6 | E | H, H i le L | Fa'amalo | |
| 7–14 | DB0–DB7 | H/L | Pasi fa'amatalaga—komepiuta e mafai ona filifilia 4-bit po'o le 8-bit mode | |
Mo nisi fa'amatalaga e pei o le taimi, fa'afanua o tagata, ta'iala o feso'ota'iga, ma isi fa'amaumauga fa'atatau, asiasi www.lumex.com.
Ulutala Debug
O lenei laupapa atina'e e aofia ai ulutala 2x8 debug e lua mo fa'amoemoega debug. O le FPGA I/Os auala sa'o i le ulutala mo su'ega mamanu, fa'aliga, po'o le fa'amaonia vave.
O le Siata 2–19 o lo'o aoteleina ai galuega fa'apena fa'aulu ulu, igoa fa'ailo, ma galuega.
Laulau 2–19. Debug Header Pin Tofiga, Igoa Fa'ailoga Fa'ailoga, ma Galuega (Vaega 1 o le 2)
| Komiti Fa'atonu Fa'asinomaga | Fa'ailoga Fa'ailoga Igoa | Afa VE FPGA Numera Pin | I/O Tulaga | Fa'amatalaga |
| Debug Ulutala (J15) | ||||
| 1 | HEADER_D0 | H21 | 1.5-V | Fa'ailo fa'ai'u tasi mo na'o fa'amoemoe |
| 5 | HEADER_D1 | G21 | 1.5-V | Fa'ailo fa'ai'u tasi mo na'o fa'amoemoe |
| 9 | HEADER_D2 | G22 | 1.5-V | Fa'ailo fa'ai'u tasi mo na'o fa'amoemoe |
| 13 | HEADER_D3 | E26 | 1.5-V | Fa'ailo fa'ai'u tasi mo na'o fa'amoemoe |
| 4 | HEADER_D4 | E25 | 1.5-V | Fa'ailo fa'ai'u tasi mo na'o fa'amoemoe |
| 8 | HEADER_D5 | C27 | 1.5-V | Fa'ailo fa'ai'u tasi mo na'o fa'amoemoe |
| 12 | HEADER_D6 | C26 | 1.5-V | Fa'ailo fa'ai'u tasi mo na'o fa'amoemoe |
Laulau 2–19. Debug Header Pin Tofiga, Igoa Fa'ailoga Fa'ailoga, ma Galuega (Vaega 2 o le 2)
| Komiti Fa'atonu Fa'asinomaga | Fa'ailoga Fa'ailoga Igoa | Afa VE FPGA Numera Pin | I/O Tulaga | Fa'amatalaga |
| 16 | HEADER_D7 | B27 | 1.5-V | Fa'ailo fa'ai'u tasi mo na'o fa'amoemoe |
| Debug Ulutala (J16) | ||||
| 1 ma le 2 | HEADER_P0 ma HEADER_N0 | H25 ma le H26 | 2.5-V | Fa'ailoga fa'asesega fa'afoliga mo na'o fa'amoemoega debug |
| 3 ma le 4 | HEADER_P1 ma
HEADER_N1 |
P20 ma le N20 | 2.5-V | Fa'ailoga fa'asesega fa'afoliga mo na'o fa'amoemoega debug |
| 7 ma le 8 | HEADER_P2 ma HEADER_N2 | J22 ma le J23 | 2.5-V | Fa'ailoga fa'asesega fa'afoliga mo na'o fa'amoemoega debug |
| 9 ma le 10 | HEADER_P3 ma HEADER_N3 | D28 ma le D29 | 2.5-V | Fa'ailoga fa'asesega fa'afoliga mo na'o fa'amoemoega debug |
| 13 ma le 14 | HEADER_P4 ma HEADER_N4 | E27 ma le D27 | 2.5-V | Fa'ailoga fa'asesega fa'afoliga mo na'o fa'amoemoega debug |
| 15 ma le 16 | HEADER_P5 ma HEADER_N5 | H24 ma le J25 | 2.5-V | Fa'ailoga fa'asesega fa'afoliga mo na'o fa'amoemoega debug |
Vaega ma Fesootaiga
O le vaega lea o lo'o fa'amatala ai uafu feso'ota'iga a le komiti fa'atino ma kata fa'afeso'ota'i e fa'atatau i le masini FPGA Afa. E lagolagoina e le komiti atina'e ia uafu feso'ota'iga nei:
- RS-232 UART Fa'asologa
- 10/100/1000 Ethernet
- HSMC
- USB UART
10/100/1000 Ethernet
E lagolagoina e le komiti atina'e le lua 10/100/1000 base-T Ethernet fa'aoga lua Marvell 88E1111 PHY ma Altera Triple-Speed Ethernet MegaCore MAC galuega. O feso'ota'iga PHY-to-MAC e fa'aogaina le RGMII. Ole galuega ole MAC e tatau ona tu'uina ile FPGA mo fa'aoga feso'ota'iga masani. O le Marvell 88E1111 PHY e fa'aogaina le 2.5-V ma le 1.0-V eletise eletise ma e mana'omia se 25-MHz fa'asino uati fa'aola mai se oscillator fa'apitoa. O le PHY e feso'ota'i i se fa'ata'ita'iga RJ45 fa'atasi ai ma maneta i totonu e mafai ona fa'aoga mo le fa'auluina o laina 'apamemea ma fefa'ataua'iga Ethernet.
Ata 2-7 o loʻo faʻaalia ai le RGMII fesoʻotaʻiga i le va o le FPGA (MAC) ma le Marvell 88E1111 PHY.
Ata 2–7. RGMII Feso'ota'iga i le va o FPGA (MAC) ma Marvell 88E1111 PHY
Laulau 2–20 o lo'o lisi ai le Ethernet PHY fa'aoga pine pine
Laulau 2–20. Ethernet PHY Pin Tofiga, Igoa Fa'ailoga ma Galuega (Vaega 1 o le 3)
| Komiti Fa'atonu Fa'asinomaga | Fa'ailoga Fa'ailoga Igoa | Afa VE FPGA Numera Pin | I/O Tulaga | Fa'amatalaga |
| 16 | HEADER_D7 | B27 | 1.5-V | Fa'ailo fa'ai'u tasi mo na'o fa'amoemoe |
| Debug Ulutala (J16) | ||||
| 1 ma le 2 | HEADER_P0 ma HEADER_N0 | H25 ma le H26 | 2.5-V | Fa'ailoga fa'asesega fa'afoliga mo na'o fa'amoemoega debug |
| 3 ma le 4 | HEADER_P1 ma
HEADER_N1 |
P20 ma le N20 | 2.5-V | Fa'ailoga fa'asesega fa'afoliga mo na'o fa'amoemoega debug |
| 7 ma le 8 | HEADER_P2 ma HEADER_N2 | J22 ma le J23 | 2.5-V | Fa'ailoga fa'asesega fa'afoliga mo na'o fa'amoemoega debug |
| 9 ma le 10 | HEADER_P3 ma HEADER_N3 | D28 ma le D29 | 2.5-V | Fa'ailoga fa'asesega fa'afoliga mo na'o fa'amoemoega debug |
| 13 ma le 14 | HEADER_P4 ma HEADER_N4 | E27 ma le D27 | 2.5-V | Fa'ailoga fa'asesega fa'afoliga mo na'o fa'amoemoega debug |
| 15 ma le 16 | HEADER_P5 ma HEADER_N5 | H24 ma le J25 | 2.5-V | Fa'ailoga fa'asesega fa'afoliga mo na'o fa'amoemoega debug |
Laulau 2–20. Ethernet PHY Pin Tofiga, Igoa Fa'ailoga ma Galuega (Vaega 2 o le 3)
| Komiti Fa'atonu Fa'asinomaga | Fuafuaga Fa'ailoga Igoa | Afa VE FPGA Numera Pin | I/O Tulaga | Fa'amatalaga |
| 33 | ENETA_MDI_P1 | — | 2.5-V CMOS | Fa'asalalauga fa'alagolago |
| 34 | ENETA_MDI_N1 | — | 2.5-V CMOS | Fa'asalalauga fa'alagolago |
| 39 | ENETA_MDI_P2 | — | 2.5-V CMOS | Fa'asalalauga fa'alagolago |
| 41 | ENETA_MDI_N2 | — | 2.5-V CMOS | Fa'asalalauga fa'alagolago |
| 42 | ENETA_MDI_P3 | — | 2.5-V CMOS | Fa'asalalauga fa'alagolago |
| 43 | ENETA_MDI_N3 | — | 2.5-V CMOS | Fa'asalalauga fa'alagolago |
| Ethernet PHY B (U11) | ||||
| 8 | ENETB_GTX_CLK | E28 | 2.5-V CMOS | 125-MHz RGMII felauai uati |
| 23 | ENETB_INTN | K22 | 2.5-V CMOS | Fa'alavelave le pulega pasi |
| 60 | ENETB_LED_DUPLEX | — | 2.5-V CMOS | Duplex po'o le feto'ai LED. Le fa'aaogaina |
| 70 | ENETB_LED_DUPLEX | — | 2.5-V CMOS | Duplex po'o le feto'ai LED. Le fa'aaogaina |
| 76 | ENETB_LED_LINK10 | — | 2.5-V CMOS | 10-Mb so'oga LED |
| 74 | ENETB_LED_LINK100 | — | 2.5-V CMOS | 100-Mb so'oga LED |
| 73 | ENETB_LED_LINK1000 | — | 2.5-V CMOS | 1000-Mb so'oga LED |
| 58 | ENETB_LED_RX | — | 2.5-V CMOS | RX fa'amatalaga galue LED |
| 69 | ENETB_LED_RX | — | 2.5-V CMOS | RX fa'amatalaga galue LED |
| 68 | ENETB_LED_TX | — | 2.5-V CMOS | TX fa'amatalaga galue LED |
| 25 | ENETB_MDC | A29 | 2.5-V CMOS | Uati fa'amaumauga a le pasi |
| 24 | ENETB_MDIO | L23 | 2.5-V CMOS | Fa'amaumauga a le pasi |
| 28 | ENETB_RESETN | M21 | 2.5-V CMOS | Toe setiina masini |
| 2 | ENETB_RX_CLK | R23 | 2.5-V CMOS | RGMII maua uati |
| 95 | ENETB_RX_D0 | F25 | 2.5-V CMOS | RGMII maua fa'amaumauga pasi |
| 92 | ENETB_RX_D1 | F26 | 2.5-V CMOS | RGMII maua fa'amaumauga pasi |
| 93 | ENETB_RX_D2 | R20 | 2.5-V CMOS | RGMII maua fa'amaumauga pasi |
| 91 | ENETB_RX_D3 | T21 | 2.5-V CMOS | RGMII maua fa'amaumauga pasi |
| 94 | ENETB_RX_DV | L24 | 2.5-V CMOS | E maua e le RGMII fa'amatalaga fa'amaonia |
| 11 | ENETB_TX_D0 | F29 | 2.5-V CMOS | RGMII felauaiga pasi fa'amatalaga |
| 12 | ENETB_TX_D1 | D30 | 2.5-V CMOS | RGMII felauaiga pasi fa'amatalaga |
| 14 | ENETB_TX_D2 | C30 | 2.5-V CMOS | RGMII felauaiga pasi fa'amatalaga |
| 16 | ENETB_TX_D3 | F28 | 2.5-V CMOS | RGMII felauaiga pasi fa'amatalaga |
| 9 | ENETB_TX_EN | B29 | 2.5-V CMOS | RGMII transmit enable |
| 55 | ENETB_XTAL_25MHZ | — | 2.5-V CMOS | 25-MHz RGMII felauai uati |
| 29 | ENETB_MDI_P0 | — | 2.5-V CMOS | Fa'asalalauga fa'alagolago |
| 31 | ENETB_MDI_N0 | — | 2.5-V CMOS | Fa'asalalauga fa'alagolago |
| 33 | ENETB_MDI_P1 | — | 2.5-V CMOS | Fa'asalalauga fa'alagolago |
| 34 | ENETB_MDI_N1 | — | 2.5-V CMOS | Fa'asalalauga fa'alagolago |
| 39 | ENETB_MDI_P2 | — | 2.5-V CMOS | Fa'asalalauga fa'alagolago |
| 41 | ENETB_MDI_N2 | — | 2.5-V CMOS | Fa'asalalauga fa'alagolago |
Laulau 2–20. Ethernet PHY Pin Tofiga, Igoa Fa'ailoga ma Galuega (Vaega 3 o le 3)
| Komiti Fa'atonu Fa'asinomaga | Fuafuaga Fa'ailoga Igoa | Afa VE FPGA Numera Pin | I/O Tulaga | Fa'amatalaga |
| 42 | ENETB_MDI_P3 | — | 2.5-V CMOS | Fa'asalalauga fa'alagolago |
| 43 | ENETB_MDI_N3 | — | 2.5-V CMOS | Fa'asalalauga fa'alagolago |
HSMC
- E lagolagoina e le komiti atina'e se atina'e HSMC. O le HSMC interface e lagolagoina le SPI4.2 interface atoa (17 LVDS channels), tolu fa'aoga ma fa'aoga uati, fa'apea ma JTAG ma faailo SMB. O alalaupapa LVDS e mafai ona faʻaogaina mo le CMOS faʻailoga poʻo le LVDS.
- O le HSMC o se faʻamatalaga tatala a Altera, lea e mafai ai e oe ona faʻalauteleina galuega a le komiti atinaʻe e ala i le faʻaopoopoga o daughtercards (HSMCs).
- Mo nisi fa'amatalaga e uiga i fa'amatalaga HSMC e pei o fa'ailoga fa'ailoga, fa'amaoni fa'ailo, feso'ota'iga fetaui, ma fa'amatalaga fa'ainisinia, va'ai i le High Speed Mezzanine Card (HSMC) Specification manual.
- O le feso'ota'iga HSMC o lo'o i ai le aofa'i o pine e 172, e aofia ai pine fa'ailo e 120, pine eletise 39, ma pine e 13. O pine o le eleele o loʻo tu i le va o laina e lua o faʻailoga ma pine eletise, e fai uma ma talipupuni ma se faʻamatalaga. O le feso'ota'iga talimalo a le HSMC e fa'avae i luga o le 0.5 mm-pitch QSH/QTH aiga o feso'ota'iga maualuga, laupapa i le laupapa mai Samtec. E tolu faletupe i totonu o lenei fesoʻotaʻiga. O le Faletupe 1 ua aveese uma pine lona tolu e pei ona faia i le QSH-DP/QTH-DP faasologa. Faletupe 2 ma le faletupe 3 o loʻo faʻapipiʻi uma pine e pei ona faia i le QSH/QTH faasologa. Talu ai o le Afa VE FPGA atina'e laupapa e le o se transceiver laupapa, o le transceiver pine o le HSMC e le fesootai i le Afa VE FPGA masini.
O le ata 2–8 o lo'o fa'aalia ai le fa'atulagaina o fa'ailoga e fa'atatau i faletupe e tolu a le Samtec connector.
Ata 2–8. HSMC Signal ma le Faletupe Ata
O le HSMC interface o lo'o iai fa'ailoga I/O fa'apolokalame e mafai ona fa'aogaina e pei o le 2.5-V LVCMOS, lea e fetaui ma le 3.3-V LVTTL. O nei pine e mafai foi ona faʻaaogaina e avea ma tulaga eseese I/O e aofia ai, ae le gata i, LVDS, mini-LVDS, ma le RSDS faʻatasi ma le 17 full-duplex channels.
E pei ona ta'ua i le High Speed Mezzanine Card (HSMC) Fa'amatalaga tusi lesona, LVDS ma tulaga fa'ai'u tasi I/O e na'o le fa'amautinoa e fa'atino pe a fa'afefiloi e tusa ai ma le pine fa'ai'u tasi po'o le pine fa'aeseese lautele.
Lisi 2–21 o lo'o lisi ai le HSMC fa'aoga pine, igoa fa'ailo, ma galuega.
Laulau 2–21. HSMC Interface Pin Tofiga, Igoa Fa'ailoga Fa'ailoga, ma Galuega (Vaega 1 o le 3)
| Komiti Fa'atonu Fa'amatalaga (J7) |
Fuafuaga Fa'ailoga Igoa |
Afā V E FPGA Pin
Numera |
I/O Tulaga |
Fa'amatalaga |
| 33 | HSMC_SDA | AB22 | 2.5-V CMOS | Fa'amaumauga fa'asologa o pulega |
| 34 | HSMC_SCL | AC22 | 2.5-V CMOS | Pulega uati faasologa |
| 35 | JTAG_TCK | AC7 | 2.5-V CMOS | JTAG faailo o le uati |
| 36 | HSMC_JTAG_TMS | — | 2.5-V CMOS | JTAG ala filifili faailo |
| 37 | HSMC_JTAG_TDO | — | 2.5-V CMOS | JTAG fa'amatalaga fa'amatalaga |
| 38 | JTAC_FPGA_TDO_RETIMER | — | 2.5-V CMOS | JTAG fa'amatalaga fa'amatalaga |
| 39 | HSMC_CLK_OUT0 | AJ14 | 2.5-V CMOS | Uati CMOS tuuto i fafo |
| 40 | HSMC_CLK_IN0 | AB16 | 2.5-V CMOS | Uati CMOS tuuto i totonu |
| 41 | HSMC_D0 | AH10 | 2.5-V CMOS | Fa'apitoa CMOS I/O bit 0 |
| 42 | HSMC_D1 | AJ10 | 2.5-V CMOS | Fa'apitoa CMOS I/O bit 1 |
| 43 | HSMC_D2 | Y13 | 2.5-V CMOS | Fa'apitoa CMOS I/O bit 2 |
| 44 | HSMC_D3 | AA14 | 2.5-V CMOS | Fa'apitoa CMOS I/O bit 3 |
| 47 | HSMC_TX_D_P0 | AK27 | LVDS poʻo le 2.5-V | LVDS TX bit 0 poʻo le CMOS bit 4 |
| 48 | HSMC_RX_D_P0 | Y16 | LVDS poʻo le 2.5-V | LVDS RX bit 0 poʻo le CMOS bit 5 |
| 49 | HSMC_TX_D_N0 | AK28 | LVDS poʻo le 2.5-V | LVDS TX bit 0n poʻo le CMOS bit 6 |
| 50 | HSMC_RX_D_N0 | AA26 | LVDS poʻo le 2.5-V | LVDS RX bit 0n poʻo le CMOS bit 7 |
| 53 | HSMC_TX_D_P1 | AJ27 | LVDS poʻo le 2.5-V | LVDS TX bit 1 poʻo le CMOS bit 8 |
| 54 | HSMC_RX_D_P1 | Y17 | LVDS poʻo le 2.5-V | LVDS RX bit 1 poʻo le CMOS bit 9 |
| 55 | HSMC_TX_D_N1 | AK26 | LVDS poʻo le 2.5-V | LVDS TX bit 1n poʻo le CMOS bit 10 |
| 56 | HSMC_RX_D_N1 | Y18 | LVDS poʻo le 2.5-V | LVDS RX bit 1n poʻo le CMOS bit 11 |
| 59 | HSMC_TX_D_P2 | AG26 | LVDS poʻo le 2.5-V | LVDS TX bit 2 poʻo le CMOS bit 12 |
| 60 | HSMC_RX_D_P2 | AA18 | LVDS poʻo le 2.5-V | LVDS RX bit 2 poʻo le CMOS bit 13 |
| 61 | HSMC_TX_D_N2 | AH26 | LVDS poʻo le 2.5-V | LVDS TX bit 2n poʻo le CMOS bit 14 |
| 62 | HSMC_RX_D_N2 | AA19 | LVDS poʻo le 2.5-V | LVDS RX bit 2n poʻo le CMOS bit 15 |
| 65 | HSMC_TX_D_P3 | AJ25 | LVDS poʻo le 2.5-V | LVDS TX bit 3 poʻo le CMOS bit 16 |
| 66 | HSMC_RX_D_P3 | Y20 | LVDS poʻo le 2.5-V | LVDS RX bit 3 poʻo le CMOS bit 17 |
| 67 | HSMC_TX_D_N3 | AK25 | LVDS poʻo le 2.5-V | LVDS TX bit 3n poʻo le CMOS bit 18 |
| 68 | HSMC_RX_D_N3 | AA20 | LVDS poʻo le 2.5-V | LVDS RX bit 3n poʻo le CMOS bit 19 |
| 71 | HSMC_TX_D_P4 | AH24 | LVDS poʻo le 2.5-V | LVDS TX bit 4 poʻo le CMOS bit 20 |
Laulau 2–21. HSMC Interface Pin Tofiga, Igoa Fa'ailoga Fa'ailoga, ma Galuega (Vaega 2 o le 3)
| Komiti Fa'atonu Fa'amatalaga (J7) |
Fuafuaga Fa'ailoga Igoa |
Afā V E FPGA Pin
Numera |
I/O Tulaga |
Fa'amatalaga |
| 72 | HSMC_RX_D_P4 | AA21 | LVDS poʻo le 2.5-V | LVDS RX bit 4 poʻo le CMOS bit 21 |
| 73 | HSMC_TX_D_N4 | AJ24 | LVDS poʻo le 2.5-V | LVDS TX bit 4n poʻo le CMOS bit 22 |
| 74 | HSMC_RX_D_N4 | AB21 | LVDS poʻo le 2.5-V | LVDS RX bit 4n poʻo le CMOS bit 23 |
| 77 | HSMC_TX_D_P5 | AH21 | LVDS poʻo le 2.5-V | LVDS TX bit 5 poʻo le CMOS bit 24 |
| 78 | HSMC_RX_D_P5 | AB19 | LVDS poʻo le 2.5-V | LVDS RX bit 5 poʻo le CMOS bit 25 |
| 79 | HSMC_TX_D_N5 | AJ22 | LVDS poʻo le 2.5-V | LVDS TX bit 5n poʻo le CMOS bit 26 |
| 80 | HSMC_RX_D_N5 | AC19 | LVDS poʻo le 2.5-V | LVDS RX bit 5n poʻo le CMOS bit 27 |
| 83 | HSMC_TX_D_P6 | AJ23 | LVDS poʻo le 2.5-V | LVDS TX bit 6 poʻo le CMOS bit 28 |
| 84 | HSMC_RX_D_P6 | AC21 | LVDS poʻo le 2.5-V | LVDS RX bit 6 poʻo le CMOS bit 29 |
| 85 | HSMC_TX_D_N6 | AK23 | LVDS poʻo le 2.5-V | LVDS TX bit 6n poʻo le CMOS bit 30 |
| 86 | HSMC_RX_D_N6 | AD20 | LVDS poʻo le 2.5-V | LVDS RX bit 6n poʻo le CMOS bit 31 |
| 89 | HSMC_TX_D_P7 | AK21 | LVDS poʻo le 2.5-V | LVDS TX bit 7 poʻo le CMOS bit 32 |
| 90 | HSMC_RX_D_P7 | AD19 | LVDS poʻo le 2.5-V | LVDS RX bit 7 poʻo le CMOS bit 33 |
| 91 | HSMC_TX_D_N7 | AK22 | LVDS poʻo le 2.5-V | LVDS TX bit 7n poʻo le CMOS bit 34 |
| 92 | HSMC_RX_D_N7 | AE20 | LVDS poʻo le 2.5-V | LVDS RX bit 7n poʻo le CMOS bit 35 |
| 95 | HSMC_CLK_OUT_P1 | AE22 | LVDS poʻo le 2.5-V | LVDS po'o le CMOS uati i fafo 1 po'o le CMOS bit 36 |
| 96 | HSMC_CLK_IN_P1 | AB14 | LVDS poʻo le 2.5-V | LVDS po'o le CMOS uati ile 1 po'o le CMOS bit 37 |
| 97 | HSMC_CLK_OUT_N1 | AF23 | LVDS poʻo le 2.5-V | LVDS po'o le CMOS uati i fafo 1 po'o le CMOS bit 38 |
| 98 | HSMC_CLK_IN_N1 | AC14 | LVDS poʻo le 2.5-V | LVDS po'o le CMOS uati ile 1 po'o le CMOS bit 39 |
| 101 | HSMC_TX_D_P8 | AJ20 | LVDS poʻo le 2.5-V | LVDS TX bit 8 poʻo le CMOS bit 40 |
| 102 | HSMC_RX_D_P8 | AF21 | LVDS poʻo le 2.5-V | LVDS RX bit 8 poʻo le CMOS bit 41 |
| 103 | HSMC_TX_D_N8 | AK20 | LVDS poʻo le 2.5-V | LVDS TX bit 8n poʻo le CMOS bit 42 |
| 104 | HSMC_RX_D_N8 | AG22 | LVDS poʻo le 2.5-V | LVDS RX bit 8n poʻo le CMOS bit 43 |
| 107 | HSMC_TX_D_P9 | AJ19 | LVDS poʻo le 2.5-V | LVDS TX bit 9 poʻo le CMOS bit 44 |
| 108 | HSMC_RX_D_P9 | AF20 | LVDS poʻo le 2.5-V | LVDS RX bit 9 poʻo le CMOS bit 45 |
| 109 | HSMC_TX_D_N9 | AK18 | LVDS poʻo le 2.5-V | LVDS TX bit 9n poʻo le CMOS bit 46 |
| 110 | HSMC_RX_D_N9 | AG21 | LVDS poʻo le 2.5-V | LVDS RX bit 9n poʻo le CMOS bit 47 |
| 113 | HSMC_TX_D_P10 | AJ17 | LVDS poʻo le 2.5-V | LVDS TX bit 10 poʻo le CMOS bit 48 |
| 114 | HSMC_RX_D_P10 | AF18 | LVDS poʻo le 2.5-V | LVDS RX bit 10 poʻo le CMOS bit 49 |
| 115 | HSMC_TX_D_N10 | AJ18 | LVDS poʻo le 2.5-V | LVDS TX bit 10n poʻo le CMOS bit 50 |
| 116 | HSMC_RX_D_N10 | AF19 | LVDS poʻo le 2.5-V | LVDS RX bit 10n poʻo le CMOS bit 51 |
| 119 | HSMC_TX_D_P11 | AK25 | LVDS poʻo le 2.5-V | LVDS TX bit 11 poʻo le CMOS bit 52 |
| 120 | HSMC_RX_D_P11 | AG18 | LVDS poʻo le 2.5-V | LVDS RX bit 11 poʻo le CMOS bit 53 |
| 121 | HSMC_TX_D_N11 | AG24 | LVDS poʻo le 2.5-V | LVDS TX bit 11n poʻo le CMOS bit 54 |
| 122 | HSMC_RX_D_N11 | AG19 | LVDS poʻo le 2.5-V | LVDS RX bit 11n poʻo le CMOS bit 55 |
| 125 | HSMC_TX_D_P12 | AH19 | LVDS poʻo le 2.5-V | LVDS TX bit 12 poʻo le CMOS bit 56 |
| 126 | HSMC_RX_D_P12 | AK16 | LVDS poʻo le 2.5-V | LVDS RX bit 12 poʻo le CMOS bit 57 |
| 127 | HSMC_TX_D_N12 | AH20 | LVDS poʻo le 2.5-V | LVDS TX bit 12n poʻo le CMOS bit 58 |
Laulau 2–21. HSMC Interface Pin Tofiga, Igoa Fa'ailoga Fa'ailoga, ma Galuega (Vaega 3 o le 3)
| Komiti Fa'atonu Fa'amatalaga (J7) |
Fuafuaga Fa'ailoga Igoa |
Afā V E FPGA Pin
Numera |
I/O Tulaga |
Fa'amatalaga |
| 128 | HSMC_RX_D_N12 | AK17 | LVDS poʻo le 2.5-V | LVDS RX bit 12n poʻo le CMOS bit 59 |
| 131 | HSMC_TX_D_P13 | AG17 | LVDS poʻo le 2.5-V | LVDS TX bit 13 poʻo le CMOS bit 60 |
| 132 | HSMC_RX_D_P13 | AF16 | LVDS poʻo le 2.5-V | LVDS RX bit 13 poʻo le CMOS bit 61 |
| 133 | HSMC_TX_D_N13 | AH17 | LVDS poʻo le 2.5-V | LVDS TX bit 13n poʻo le CMOS bit 62 |
| 134 | HSMC_RX_D_N13 | AG16 | LVDS poʻo le 2.5-V | LVDS RX bit 13n poʻo le CMOS bit 63 |
| 137 | HSMC_TX_D_P14 | AJ15 | LVDS poʻo le 2.5-V | LVDS TX bit 14 poʻo le CMOS bit 64 |
| 138 | HSMC_RX_D_P14 | AE16 | LVDS poʻo le 2.5-V | LVDS RX bit 14 poʻo le CMOS bit 65 |
| 139 | HSMC_TX_D_N14 | AK15 | LVDS poʻo le 2.5-V | LVDS TX bit 14n poʻo le CMOS bit 66 |
| 140 | HSMC_RX_D_N14 | AF15 | LVDS poʻo le 2.5-V | LVDS RX bit 14n poʻo le CMOS bit 67 |
| 143 | HSMC_TX_D_P15 | AH14 | LVDS poʻo le 2.5-V | LVDS TX bit 15 poʻo le CMOS bit 68 |
| 144 | HSMC_RX_D_P15 | AD17 | LVDS poʻo le 2.5-V | LVDS RX bit 15 poʻo le CMOS bit 69 |
| 145 | HSMC_TX_D_N15 | AH15 | LVDS poʻo le 2.5-V | LVDS TX bit 15n poʻo le CMOS bit 70 |
| 146 | HSMC_RX_D_N15 | AE17 | LVDS poʻo le 2.5-V | LVDS RX bit 15n poʻo le CMOS bit 71 |
| 149 | HSMC_TX_D_P16 | AE15 | LVDS poʻo le 2.5-V | LVDS TX bit 16 poʻo le CMOS bit 72 |
| 150 | HSMC_RX_D_P16 | AD18 | LVDS poʻo le 2.5-V | LVDS RX bit 16 poʻo le CMOS bit 73 |
| 151 | HSMC_TX_D_N16 | AF14 | LVDS poʻo le 2.5-V | LVDS TX bit 16n poʻo le CMOS bit 74 |
| 152 | HSMC_RX_D_N16 | AE18 | LVDS poʻo le 2.5-V | LVDS RX bit 16n poʻo le CMOS bit 75 |
| 155 | HSMC_CLK_OUT_P2 | AG23 | LVDS poʻo le 2.5-V | LVDS po'o le CMOS uati i fafo 2 po'o le CMOS bit 76 |
| 156 | HSMC_CLK_IN_P2 | Y15 | LVDS poʻo le 2.5-V | LVDS po'o le CMOS uati ile 2 po'o le CMOS bit 77 |
| 157 | HSMC_CLK_OUT_N2 | AH22 | LVDS poʻo le 2.5-V | LVDS po'o le CMOS uati i fafo 2 po'o le CMOS bit 78 |
| 158 | HSMC_CLK_IN_N2 | AA15 | LVDS poʻo le 2.5-V | LVDS po'o le CMOS uati ile 2 po'o le CMOS bit 79 |
| 160 | HSMC_PRSNTn | AK5 | 2.5-V CMOS | HSMC uafu i ai iloa |
RS-232 UART Fa'asologa
O le DSUB 9-pin feso'ota'iga tama'ita'i fa'atasi ai ma le feso'ota'iga RS-232 lagolago e tu'uina atu ai le lagolago mo le fa'atinoina o se alalaupapa UART masani RS-232 i luga o lenei laupapa. O le feso'ota'iga e tutusa pine e pei o se masini fa'amaumauga ma e mana'omia na'o se uaea masani (leai se modem null e mana'omia mo le PC interface). O lo'o fa'aaogaina se pa'u fa'asolo fa'apitoa e fa'aliliu ai le va o le LVTTL ma le RS-232. O fa'amatalaga a le Komiti D23 ma le D24 o fa'asologa UART LED e fa'amalamalamaina e fa'ailoa ai le gaioiga RX ma le TX.
Lisi 2–24 o lo'o lisi ai le RS-232 fa'asologa o pine UART, igoa fa'ailo, ma galuega.
O igoa fa'ailo ma ituaiga e fa'atatau ile Afa VE FPGA ile tulaga ole fa'atulagaina ole I/O ma le fa'atonuga.
Laulau 2–22. RS-232 Serial UART Schematic Signal Names and Functions
| Komiti Fa'atonu Fa'asinoga (U20) | Fuafuaga Fa'ailoga Igoa | Afa VE FPGA Numera Pin | I/O Tulaga | Fa'amatalaga |
| 14 | UART_TXD | AB9 | 3.3-V | Fa'asalalau fa'amatalaga |
| 15 | UART_RTS | AH6 | 3.3-V | Talosaga e lafo |
Laulau 2–22. RS-232 Serial UART Schematic Signal Names and Functions
| Komiti Fa'atonu Fa'asinoga (U20) | Fuafuaga Fa'ailoga Igoa | Afa VE FPGA Numera Pin | I/O Tulaga | Fa'amatalaga |
| 16 | UART_RXD | AG6 | 3.3-V | Maua faʻamatalaga |
| 13 | UART_CTS | AF8 | 3.3-V | Fa'amanino e lafo |
USB-UART
E lagolagoina e le komiti atina'e le UART interface e ala i se feso'ota'iga USB e fa'aaoga ai le alalaupapa Silicon Labs CP2104 USB-to-UART. Ina ia fa'afaigofie feso'ota'iga talimalo ma le CP2104, e mana'omia lou fa'aogaina o le USB-to-UART bridge Virtual COM Port (VCP) aveta'avale.
O lo'o maua aveta'avale VCP ile: www.silabs.com/products/mcu/Pages/USBtoUARTBridgeVCPDrivers.aspx
Lisi 2–23 o lo'o lisiina ai le fa'auigaina o pine USB-UART, igoa fa'ailo, ma galuega. O igoa fa'ailo ma ituaiga e fa'atatau ile Afa VE FPGA ile tulaga ole fa'atulagaina ole I/O ma le fa'atonuga
Laulau 2–23. USB-UART Schematic Signal Igoa ma Galuega
| Komiti Fa'atonu Fa'asinoga (U20) | Fuafuaga Fa'ailoga Igoa | Afa VE FPGA Numera Pin | I/O Tulaga | Fa'amatalaga |
| 1 | USB_UART_RI | AD12 | 2.5-V | Fa'ailo fa'atonutonu fa'ailoga mama (mau'alalo gaioi) |
| 24 | USB_UART_DCD | AD13 | 2.5-V | E iloa e le ave fa'amatalaga mea e fa'aoga ai le fa'atonu (maualalo malosi) |
| 22 | USB_UART_DSR | V12 | 2.5-V | Seti fa'amatalaga fa'atonu fa'aoga (gaoioiga maualalo) |
| 21 | USB_UART_RXD | AF10 | 2.5-V | Tuuina atu o fa'amatalaga e le'i fa'atasi (UART maua) |
| 19 | USB_UART_RTS | AE12 | 2.5-V | Sauni e lafo fa'atonu mea fa'atino (gaoioiga maualalo) |
| 12 | USB_UART_GPIO2 | AE13 | 2.5-V | Fa'aoga-fa'aoga mea fa'aoga po'o mea e fai. |
| 23 | USB_UART_DTR | AE10 | 2.5-V | Fa'amatalaga fa'amau fa'atonuga fa'atonuga (gaoioiga maualalo) |
| 20 | USB_UART_TXD | W12 | 2.5-V | Tuuina atu o fa'amatalaga e le fa'aogaina (UART transmit) |
| 18 | USB_UART_CTS | AJ1 | 2.5-V | Fa'amanino e lafo le fa'aoga fa'atonutonu (galue maualalo) |
| 15 | USB_UART_SUSPENDn | — | 2.5-V | E maualalo le pine pe a o'o le CP2104 i le tulaga fa'agata USB. |
| 17 | USB_UART_SUSPEND | — | 2.5-V | E maualuga le pine pe a o'o le CP2104 i le tulaga fa'agata USB. |
| 9 | USB_UART_RSTn | — | 2.5-V | Toe setiina masini |
Manatu
O le vaega lea o lo'o fa'amatalaina ai le lagolago a le komiti fa'ata'atitia fa'atasi ma latou igoa fa'ailo, ituaiga, ma feso'ota'iga e fa'atatau i le Afa VE FPGA. O le laupapa atina'e o lo'o i ai feso'ota'iga manatua nei:
- DDR3 SDRAM
- LPDDR2 SDRAM
- EEPROM
- SRAM fa'atasi
- Emo fa'atasi
Mo nisi fa'amatalaga e uiga i feso'ota'iga manatua, va'ai i pepa nei:
- Vaega o Su'esu'ega Taimi i totonu o le Tusitaulima Fa'amatalaga Fa'amatalaga Fafo.
- DDR, DDR2, ma DDR3 SDRAM Design Tutorials vaega i totonu o le Tusitaulima Faʻamatalaga Faʻamatalaga Fafo.
DDR3 SDRAM
- E lagolagoina e le komiti atina'e le lua 16Mx16x8 ma lua 16Mx8x8 DDR3 SDRAM feso'ota'iga mo le maualuga-saosaoa fa'asologa fa'asologa o manatuaga.
- O le pasi fa'amaumauga 32-bit e aofia ai masini x16 e lua e fa'aogaina ai le fa'aoga vaivai (SMC). Faatasi ai ma le SMC, o lenei atinaʻe manatua e tamoʻe i se faʻasologa masani o le 300 MHz mo le maualuga o le bandwidth faʻataʻitaʻiga o luga ole 9.6 Gbps. Ole maualuga ole taimi ole masini DDR3 ole 800MHz ma le CAS latency ole 11.
- Laulau 2–24 o lo'o lisi ai pine DDR3, igoa fa'ailo, ma galuega. O igoa fa'ailo ma ituaiga e fa'atatau ile Afa VE FPGA ile tulaga ole fa'atulagaina ole I/O ma le fa'atonuga.
Laulau 2–24. DDR3 Mea Fa'atonu Pin, Igoa Fa'ailoga Fa'ailoga, ma Galuega (Vaega 1 o le 4)
| Komiti Fa'atonu Fa'asinomaga | Fuafuaga Fa'ailoga Igoa | Afa VE FPGA Numera Pin | I/O Tulaga | Fa'amatalaga |
| DDR3 x16 (U8) | ||||
| N3 | DDR3_A0 | A16 | 1.5-V SSTL Vasega I | Tulaga pasi |
| P7 | DDR3_A1 | G23 | 1.5-V SSTL Vasega I | Tulaga pasi |
| P3 | DDR3_A2 | E21 | 1.5-V SSTL Vasega I | Tulaga pasi |
| N2 | DDR3_A3 | E22 | 1.5-V SSTL Vasega I | Tulaga pasi |
| P8 | DDR3_A4 | A20 | 1.5-V SSTL Vasega I | Tulaga pasi |
| P2 | DDR3_A5 | A26 | 1.5-V SSTL Vasega I | Tulaga pasi |
| R8 | DDR3_A6 | A15 | 1.5-V SSTL Vasega I | Tulaga pasi |
| R2 | DDR3_A7 | B26 | 1.5-V SSTL Vasega I | Tulaga pasi |
| T8 | DDR3_A8 | H17 | 1.5-V SSTL Vasega I | Tulaga pasi |
| R3 | DDR3_A9 | D14 | 1.5-V SSTL Vasega I | Tulaga pasi |
| L7 | DDR3_A10 | E23 | 1.5-V SSTL Vasega I | Tulaga pasi |
Laulau 2–24. DDR3 Mea Fa'atonu Pin, Igoa Fa'ailoga Fa'ailoga, ma Galuega (Vaega 2 o le 4)
| Komiti Fa'atonu Fa'asinomaga | Fuafuaga Fa'ailoga Igoa | Afa VE FPGA Numera Pin | I/O Tulaga | Fa'amatalaga |
| R7 | DDR3_A11 | E20 | 1.5-V SSTL Vasega I | Tulaga pasi |
| N7 | DDR3_A12 | C25 | 1.5-V SSTL Vasega I | Tulaga pasi |
| T3 | DDR3_A13 | B13 | 1.5-V SSTL Vasega I | Tulaga pasi |
| M2 | DDR3_BA0 | J18 | 1.5-V SSTL Vasega I | pasi tuatusi faletupe |
| N8 | DDR3_BA1 | F20 | 1.5-V SSTL Vasega I | pasi tuatusi faletupe |
| M3 | DDR3_BA2 | D19 | 1.5-V SSTL Vasega I | pasi tuatusi faletupe |
| K3 | DDR3_CASN | L20 | 1.5-V SSTL Vasega I | Filifili le tuatusi o le laina |
| K9 | DDR3_CKE | C11 | 1.5-V SSTL Vasega I | Filifilia tuatusi tuatusi |
| J7 | DDR3_CLK_P | J20 | Eseesega 1.5-V SSTL Vasega I | Uati gaosiga eseese |
| K7 | DDR3_CLK_N | H20 | Eseesega 1.5-V SSTL Vasega I | Uati gaosiga eseese |
| L2 | DDR3_CSN | G17 | 1.5-V SSTL Vasega I | Filifili Chip |
| E7 | DDR3_DM0 | D23 | 1.5-V SSTL Vasega I | Tusi le ala mask byte |
| D3 | DDR3_DM1 | D18 | 1.5-V SSTL Vasega I | Tusi le ala mask byte |
| E3 | DDR3_DQ0 | A25 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 0 |
| H8 | DDR3_DQ1 | D22 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 0 |
| F7 | DDR3_DQ2 | C21 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 0 |
| H7 | DDR3_DQ3 | C19 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 0 |
| F2 | DDR3_DQ4 | C20 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 0 |
| G2 | DDR3_DQ5 | C22 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 0 |
| F8 | DDR3_DQ6 | D25 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 0 |
| H3 | DDR3_DQ7 | D20 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 0 |
| A7 | DDR3_DQ8 | B24 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 1 |
| C3 | DDR3_DQ9 | A21 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 1 |
| A3 | DDR3_DQ10 | B21 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 1 |
| D7 | DDR3_DQ11 | F19 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 1 |
| A2 | DDR3_DQ12 | C24 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 1 |
| C2 | DDR3_DQ13 | B23 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 1 |
| B8 | DDR3_DQ14 | E18 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 1 |
| C8 | DDR3_DQ15 | A23 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 1 |
| F3 | DDR3_DQS_P0 | K20 | Eseesega 1.5-V SSTL Vasega I | Fa'amatalaga strobe P byte laina 0 |
| G3 | DDR3_DQS_N0 | J19 | Eseesega 1.5-V SSTL Vasega I | Fa'amatalaga strobe N byte laina 0 |
| C7 | DDR3_DQS_P1 | L18 | Eseesega 1.5-V SSTL Vasega I | Fa'amatalaga strobe P byte laina 1 |
| B7 | DDR3_DQS_N1 | K18 | Eseesega 1.5-V SSTL Vasega I | Fa'amatalaga strobe N byte laina 1 |
| K1 | DDR3_ODT | H19 | 1.5-V SSTL Vasega I | Fa'agata fa'agata e mafai |
Laulau 2–24. DDR3 Mea Fa'atonu Pin, Igoa Fa'ailoga Fa'ailoga, ma Galuega (Vaega 3 o le 4)
| Komiti Fa'atonu Fa'asinomaga | Fuafuaga Fa'ailoga Igoa | Afa VE FPGA Numera Pin | I/O Tulaga | Fa'amatalaga |
| J3 | DDR3_RASN | A24 | 1.5-V SSTL Vasega I | Filifili le tuatusi o le laina |
| T2 | DDR3_RESETN | L19 | 1.5-V SSTL Vasega I | Toe setiina |
| L3 | DDR3_WEN | B22 | 1.5-V SSTL Vasega I | Tusi le mafai |
| L8 | DDR3_ZQ01 | — | 1.5-V SSTL Vasega I | ZQ impedance calibration |
| DDR3 x16 (U7) | ||||
| N3 | DDR3_A0 | A16 | 1.5-V SSTL Vasega I | Tulaga pasi |
| P7 | DDR3_A1 | G23 | 1.5-V SSTL Vasega I | Tulaga pasi |
| P3 | DDR3_A2 | E21 | 1.5-V SSTL Vasega I | Tulaga pasi |
| N2 | DDR3_A3 | E22 | 1.5-V SSTL Vasega I | Tulaga pasi |
| P8 | DDR3_A4 | A20 | 1.5-V SSTL Vasega I | Tulaga pasi |
| P2 | DDR3_A5 | A26 | 1.5-V SSTL Vasega I | Tulaga pasi |
| R8 | DDR3_A6 | A15 | 1.5-V SSTL Vasega I | Tulaga pasi |
| R2 | DDR3_A7 | B26 | 1.5-V SSTL Vasega I | Tulaga pasi |
| T8 | DDR3_A8 | H17 | 1.5-V SSTL Vasega I | Tulaga pasi |
| R3 | DDR3_A9 | D14 | 1.5-V SSTL Vasega I | Tulaga pasi |
| L7 | DDR3_A10 | E23 | 1.5-V SSTL Vasega I | Tulaga pasi |
| R7 | DDR3_A11 | E20 | 1.5-V SSTL Vasega I | Tulaga pasi |
| N7 | DDR3_A12 | C25 | 1.5-V SSTL Vasega I | Tulaga pasi |
| T3 | DDR3_A13 | B13 | 1.5-V SSTL Vasega I | Tulaga pasi |
| M2 | DDR3_BA0 | J18 | 1.5-V SSTL Vasega I | pasi tuatusi faletupe |
| N8 | DDR3_BA1 | F20 | 1.5-V SSTL Vasega I | pasi tuatusi faletupe |
| M3 | DDR3_BA2 | D19 | 1.5-V SSTL Vasega I | pasi tuatusi faletupe |
| K3 | DDR3_CASN | L20 | 1.5-V SSTL Vasega I | Filifili le tuatusi o le laina |
| K9 | DDR3_CKE | AK18 | 1.5-V SSTL Vasega I | Filifilia tuatusi tuatusi |
| K7 | DDR3_CLK_P | J20 | 1.5-V SSTL Vasega I | Uati gaosiga eseese |
| J7 | DDR3_CLK_N | H20 | 1.5-V SSTL Vasega I | Uati gaosiga eseese |
| L2 | DDR3_CSN | G17 | 1.5-V SSTL Vasega I | Filifili Chip |
| E7 | DDR3_DM2 | A19 | 1.5-V SSTL Vasega I | Tusi le ala mask byte |
| D3 | DDR3_DM3 | B14 | 1.5-V SSTL Vasega I | Tusi le ala mask byte |
| F2 | DDR3_DQ16 | G18 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 2 |
| F8 | DDR3_DQ17 | B18 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 2 |
| E3 | DDR3_DQ18 | A18 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 2 |
| F7 | DDR3_DQ19 | F18 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 2 |
| H3 | DDR3_DQ20 | C14 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 2 |
| G2 | DDR3_DQ21 | C17 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 2 |
| H7 | DDR3_DQ22 | B17 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 2 |
| H8 | DDR3_DQ23 | B19 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 2 |
| A2 | DDR3_DQ24 | C15 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 3 |
Laulau 2–24. DDR3 Mea Fa'atonu Pin, Igoa Fa'ailoga Fa'ailoga, ma Galuega (Vaega 4 o le 4)
| Komiti Fa'atonu Fa'asinomaga | Fuafuaga Fa'ailoga Igoa | Afa VE FPGA Numera Pin | I/O Tulaga | Fa'amatalaga |
| C2 | DDR3_DQ25 | D17 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 3 |
| D7 | DDR3_DQ26 | C12 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 3 |
| A7 | DDR3_DQ27 | E17 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 3 |
| A3 | DDR3_DQ28 | C16 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 3 |
| C3 | DDR3_DQ29 | A14 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 3 |
| B8 | DDR3_DQ30 | D12 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 3 |
| C8 | DDR3_DQ31 | A13 | 1.5-V SSTL Vasega I | Fa'amatalaga pasi ala ala 3 |
| F3 | DDR3_DQS_P2 | K16 | Eseesega 1.5-V SSTL Vasega I | Fa'amatalaga strobe P byte laina 2 |
| G3 | DDR3_DQS_N2 | L16 | Eseesega 1.5-V SSTL Vasega I | Fa'amatalaga strobe N byte laina 2 |
| C7 | DDR3_DQS_P3 | K17 | Eseesega 1.5-V SSTL Vasega I | Fa'amatalaga strobe P byte laina 3 |
| B7 | DDR3_DQS_N3 | J17 | Eseesega 1.5-V SSTL Vasega I | Fa'amatalaga strobe N byte laina 3 |
| K1 | DDR3_ODT | H19 | 1.5-V SSTL Vasega I | Fa'agata fa'agata e mafai |
| J3 | DDR3_RASN | A24 | 1.5-V SSTL Vasega I | Filifili le tuatusi o le laina |
| T2 | DDR3_RESETN | L19 | 1.5-V SSTL Vasega I | Toe setiina |
| L3 | DDR3_WEN | B22 | 1.5-V SSTL Vasega I | Tusi le mafai |
| L8 | DDR3_ZQ2 | — | 1.5-V SSTL Vasega I | ZQ impedance calibration |
LPDDR2 SDRAM
O le LPDDR2 o se masini feaveaʻi DDR2 SDRAM telefoni feaveaʻi e faʻaogaina i le 1.2 V. O lenei faʻaoga e fesoʻotaʻi atu i faletupe I / O faʻalava i luga o le pito i luga ole masini FPGA.
Ole saoasaoa ole masini ole 300MHz. E naʻo le x16 faʻaoga e faʻaaogaina e ui o le LPDDR2 SDRAM i luga o le laupapa o se masini x32.
Laulau 2–25 o lo'o lisi ai le LPDDR2 SDRAM pine, igoa fa'ailo, ma galuega.
O igoa fa'ailo ma ituaiga e fa'atatau ile Afa VE FPGA ile tulaga ole fa'atulagaina ole I/O ma le fa'atonuga.
Laulau 2–25. LPDDR2 SDRAM Igoa Fa'ailoga Fa'ailoga ma Galuega
| Komiti Fa'atonu Fa'asinoga (U9) | Fuafuaga Fa'ailoga Igoa | Afa VE Numera Pin FPGA | I/O Tulaga | Fa'amatalaga |
| AC6 | LPDDR2_CA0 | Y30 | 1.2-V HSUL | Tulaga pasi |
| AB6 | LPDDR2_CA1 | T30 | 1.2-V HSUL | Tulaga pasi |
| AC7 | LPDDR2_CA2 | W29 | 1.2-V HSUL | Tulaga pasi |
| AB8 | LPDDR2_CA3 | AB29 | 1.2-V HSUL | Tulaga pasi |
| AB9 | LPDDR2_CA4 | W30 | 1.2-V HSUL | Tulaga pasi |
| W1 | LPDDR2_CA5 | U29 | 1.2-V HSUL | Tulaga pasi |
| V2 | LPDDR2_CA6 | AC30 | 1.2-V HSUL | Tulaga pasi |
| U1 | LPDDR2_CA7 | R30 | 1.2-V HSUL | Tulaga pasi |
Laulau 2–25. LPDDR2 SDRAM Igoa Fa'ailoga Fa'ailoga ma Galuega
| Komiti Fa'atonu Fa'asinoga (U9) | Fuafuaga Fa'ailoga Igoa | Afa VE Numera Pin FPGA | I/O Tulaga | Fa'amatalaga |
| T2 | LPDDR2_CA8 | T28 | 1.2-V HSUL | Tulaga pasi |
| T1 | LPDDR2_CA9 | T25 | 1.2-V HSUL | Tulaga pasi |
| Y2 | LPDDR2_CK | V21 | Eseesega 1.2-V HSUL | Uati fa'aola ese'ese P |
| Y1 | LPDDR2_CKN | V22 | Eseesega 1.2-V HSUL | Uati fa'aola ese'ese N |
| AC3 | LPDDR2_CKE | T29 | 1.2-V HSUL | Uati mafai |
| AB3 | LPDDR2_CSN | R26 | 1.2-V HSUL | Filifili Chip |
| N23 | LPDDR2_DM0 | AG29 | 1.2-V HSUL | ufimata fa'amatalaga |
| L23 | LPDDR2_DM1 | AB27 | 1.2-V HSUL | ufimata fa'amatalaga |
| AB20 | LPDDR2_DM2 | — | 1.2-V HSUL | ufimata fa'amatalaga |
| B20 | LPDDR2_DM3 | — | 1.2-V HSUL | ufimata fa'amatalaga |
| AA23 | LPDDR2_DQ0 | AG28 | 1.2-V HSUL | Fa'amatalaga pasi ala ala 0 |
| Y22 | LPDDR2_DQ1 | AH30 | 1.2-V HSUL | Fa'amatalaga pasi ala ala 0 |
| W22 | LPDDR2_DQ2 | AA28 | 1.2-V HSUL | Fa'amatalaga pasi ala ala 0 |
| W23 | LPDDR2_DQ3 | AH29 | 1.2-V HSUL | Fa'amatalaga pasi ala ala 0 |
| V23 | LPDDR2_DQ4 | Y28 | 1.2-V HSUL | Fa'amatalaga pasi ala ala 0 |
| U22 | LPDDR2_DQ5 | AE30 | 1.2-V HSUL | Fa'amatalaga pasi ala ala 0 |
| T22 | LPDDR2_DQ6 | AJ28 | 1.2-V HSUL | Fa'amatalaga pasi ala ala 0 |
| T23 | LPDDR2_DQ7 | AD30 | 1.2-V HSUL | Fa'amatalaga pasi ala ala 0 |
| H22 | LPDDR2_DQ8 | AC29 | 1.2-V HSUL | Fa'amatalaga pasi ala ala 1 |
| H23 | LPDDR2_DQ9 | AF30 | 1.2-V HSUL | Fa'amatalaga pasi ala ala 1 |
| G23 | LPDDR2_DQ10 | AA30 | 1.2-V HSUL | Fa'amatalaga pasi ala ala 1 |
| F22 | LPDDR2_DQ11 | AE28 | 1.2-V HSUL | Fa'amatalaga pasi ala ala 1 |
| E22 | LPDDR2_DQ12 | AF29 | 1.2-V HSUL | Fa'amatalaga pasi ala ala 1 |
| E23 | LPDDR2_DQ13 | AD28 | 1.2-V HSUL | Fa'amatalaga pasi ala ala 1 |
| D23 | LPDDR2_DQ14 | V27 | 1.2-V HSUL | Fa'amatalaga pasi ala ala 1 |
| C22 | LPDDR2_DQ15 | W28 | 1.2-V HSUL | Fa'amatalaga pasi ala ala 1 |
| AB12 | LPDDR2_DQ16 | — | 1.2-V HSUL | Fa'amatalaga pasi ala ala 2 |
| AC13 | LPDDR2_DQ17 | — | 1.2-V HSUL | Fa'amatalaga pasi ala ala 2 |
| AB14 | LPDDR2_DQ18 | — | 1.2-V HSUL | Fa'amatalaga pasi ala ala 2 |
| AC14 | LPDDR2_DQ19 | — | 1.2-V HSUL | Fa'amatalaga pasi ala ala 2 |
| AB15 | LPDDR2_DQ20 | — | 1.2-V HSUL | Fa'amatalaga pasi ala ala 2 |
| AC16 | LPDDR2_DQ21 | — | 1.2-V HSUL | Fa'amatalaga pasi ala ala 2 |
| AB17 | LPDDR2_DQ22 | — | 1.2-V HSUL | Fa'amatalaga pasi ala ala 2 |
| AC17 | LPDDR2_DQ23 | — | 1.2-V HSUL | Fa'amatalaga pasi ala ala 2 |
| B17 | LPDDR2_DQ24 | — | 1.2-V HSUL | Fa'amatalaga pasi ala ala 3 |
| A17 | LPDDR2_DQ25 | — | 1.2-V HSUL | Fa'amatalaga pasi ala ala 3 |
| A16 | LPDDR2_DQ26 | — | 1.2-V HSUL | Fa'amatalaga pasi ala ala 3 |
| B15 | LPDDR2_DQ27 | — | 1.2-V HSUL | Fa'amatalaga pasi ala ala 3 |
| B14 | LPDDR2_DQ28 | — | 1.2-V HSUL | Fa'amatalaga pasi ala ala 3 |
Laulau 2–25. LPDDR2 SDRAM Igoa Fa'ailoga Fa'ailoga ma Galuega
| Komiti Fa'atonu Fa'asinoga (U9) | Fuafuaga Fa'ailoga Igoa | Afa VE Numera Pin FPGA | I/O Tulaga | Fa'amatalaga |
| A14 | LPDDR2_DQ29 | — | 1.2-V HSUL | Fa'amatalaga pasi ala ala 3 |
| A13 | LPDDR2_DQ30 | — | 1.2-V HSUL | Fa'amatalaga pasi ala ala 3 |
| B12 | LPDDR2_DQ31 | — | 1.2-V HSUL | Fa'amatalaga pasi ala ala 3 |
| R23 | LPDDR2_DQS0 | V26 | Eseesega 1.2-V HSUL | Fa'amatalaga strobe P byte laina 0 |
| P22 | LPDDR2_DQSN0 | U26 | Eseesega 1.2-V HSUL | Fa'amatalaga strobe N byte laina 0 |
| J22 | LPDDR2_DQS1 | U27 | Eseesega 1.2-V HSUL | Fa'amatalaga strobe P byte laina 1 |
| K23 | LPDDR2_DQSN1 | U28 | Eseesega 1.2-V HSUL | Fa'amatalaga strobe N byte laina 1 |
| AB18 | LPDDR2_DQS2 | — | Eseesega 1.2-V HSUL | Fa'amatalaga strobe P byte laina 2 |
| AC19 | LPDDR2_DQSN2 | — | Eseesega 1.2-V HSUL | Fa'amatalaga strobe N byte laina 2 |
| B18 | LPDDR2_DQS3 | — | Eseesega 1.2-V HSUL | Fa'amatalaga strobe P byte laina 3 |
| A19 | LPDDR2_DQSN4 | — | Eseesega 1.2-V HSUL | Fa'amatalaga strobe N byte laina 3 |
| P1 | LPDDR2_ZQ | — | 1.2-V | ZQ impedance calibration |
EEPROM
O lenei laupapa e aofia ai le 64-Kb EEPROM masini. O lenei masini e iai le 2-uaea fa'asologa fa'asolosolo pasi I2C.
O le Siata 2–26 o lo'o lisiina ai galuega a pine EEPROM, igoa faailo, ma galuega. O igoa fa'ailo ma ituaiga e fa'atatau ile Afa VE FPGA ile tulaga ole fa'atulagaina ole I/O ma le fa'atonuga.
Laulau 2–26. EEPROM Schematic Signal Names and Functions
| Komiti Fa'atonu Fa'asinoga (U12) | Fuafuaga Fa'ailoga Igoa | Afa VE FPGA Numera Pin | I/O Tulaga | Fa'amatalaga |
| 1 | EEPROM_A0 | — | 3.3-V | tuatusi Chip |
| 2 | EEPROM_A1 | — | 3.3-V | tuatusi Chip |
| 3 | EEPROM_A2 | — | 3.3-V | tuatusi Chip |
| 5 | EEPROM_SDA | AH7 | 3.3-V | tuatusi fa'asologa po'o fa'amaumauga |
| 6 | EEPROM_SCL | AG7 | 3.3-V | Uati fa'asologa |
| 7 | EEPROM_WP | — | 3.3-V | Tusi mea e puipuia ai |
SRAM fa'atasi
E lagolagoina e le komiti atina'e le 18-Mb standard synchronous SRAM mo le fa'atonuga ma le teuina o fa'amaumauga ma le maualalo-latency avanoa avanoa avanoa. O le masini e iai le 1024K x 18-bits interface. O lenei masini o se vaega o le pasi FSM fefaʻasoaaʻi e fesoʻotaʻi i le flash memory, SRAM, ma MAX V CPLD 5M2210 System Controller. Ole saosaoa ole masini ole 250MHz tasi-data-rate. E leai se saoasaoa maualalo mo lenei masini. O le bandwidth faʻaupuga o lenei atinaʻe o le 4 Gbps mo faʻaauau pea. O le leo faitau mo soo se tuatusi e lua uati ae o le tusitusi e tasi le uati.
O le laulau 2–27 o lo'o lisiina ai tofitofiga pine SSRAM, igoa faailo, ma galuega.
Laulau 2–27. SSRAM Pin Tofiga, Fa'ailoga Igoa Fa'ailoga, ma Galuega (Vaega 1 o le 2)
| Komiti Fa'atonu Fa'asinoga (U11) | Fuafuaga Fa'ailoga Igoa | Afa VE FPGA Numera Pin | I/O Tulaga | Fa'amatalaga |
| 86 | SRAM_OEN | E7 | 2.5-V | Fa'atosina mafai |
| 87 | SRAM_WEN | D6 | 2.5-V | Tusi le mafai |
| 37 | FSM_A1 | B11 | 2.5-V | Tulaga pasi |
| 36 | FSM_A2 | A11 | 2.5-V | Tulaga pasi |
| 44 | FSM_A3 | D9 | 2.5-V | Tulaga pasi |
| 42 | FSM_A4 | C10 | 2.5-V | Tulaga pasi |
| 34 | FSM_A5 | A10 | 2.5-V | Tulaga pasi |
| 47 | FSM_A6 | A9 | 2.5-V | Tulaga pasi |
| 43 | FSM_A7 | C9 | 2.5-V | Tulaga pasi |
| 46 | FSM_A8 | B8 | 2.5-V | Tulaga pasi |
| 45 | FSM_A9 | B7 | 2.5-V | Tulaga pasi |
| 35 | FSM_A10 | A8 | 2.5-V | Tulaga pasi |
| 32 | FSM_A11 | B6 | 2.5-V | Tulaga pasi |
| 33 | FSM_A12 | A6 | 2.5-V | Tulaga pasi |
| 50 | FSM_A13 | C7 | 2.5-V | Tulaga pasi |
| 48 | FSM_A14 | C6 | 2.5-V | Tulaga pasi |
| 100 | FSM_A15 | F13 | 2.5-V | Tulaga pasi |
| 99 | FSM_A16 | E13 | 2.5-V | Tulaga pasi |
| 82 | FSM_A17 | A5 | 2.5-V | Tulaga pasi |
| 80 | FSM_A18 | A4 | 2.5-V | Tulaga pasi |
| 49 | FSM_A19 | J7 | 2.5-V | Tulaga pasi |
| 81 | FSM_A20 | H7 | 2.5-V | Tulaga pasi |
| 39 | FSM_A21 | J9 | 2.5-V | Tulaga pasi |
| 58 | FSM_D0 | F16 | 2.5-V | pasi fa'amatalaga |
| 59 | FSM_D1 | E16 | 2.5-V | pasi fa'amatalaga |
| 62 | FSM_D2 | M9 | 2.5-V | pasi fa'amatalaga |
| 63 | FSM_D3 | M8 | 2.5-V | pasi fa'amatalaga |
| 68 | FSM_D4 | F15 | 2.5-V | pasi fa'amatalaga |
| 69 | FSM_D5 | E15 | 2.5-V | pasi fa'amatalaga |
Laulau 2–27. SSRAM Pin Tofiga, Fa'ailoga Igoa Fa'ailoga, ma Galuega (Vaega 2 o le 2)
| Komiti Fa'atonu Fa'asinoga (U11) | Fuafuaga Fa'ailoga Igoa | Afa VE FPGA Numera Pin | I/O Tulaga | Fa'amatalaga |
| 72 | FSM_D6 | E12 | 2.5-V | pasi fa'amatalaga |
| 73 | FSM_D7 | D13 | 2.5-V | pasi fa'amatalaga |
| 23 | FSM_D8 | J15 | 2.5-V | pasi fa'amatalaga |
| 22 | FSM_D9 | H15 | 2.5-V | pasi fa'amatalaga |
| 19 | FSM_D10 | E11 | 2.5-V | pasi fa'amatalaga |
| 18 | FSM_D11 | D10 | 2.5-V | pasi fa'amatalaga |
| 12 | FSM_D12 | L10 | 2.5-V | pasi fa'amatalaga |
| 13 | FSM_D13 | L9 | 2.5-V | pasi fa'amatalaga |
| 8 | FSM_D14 | G14 | 2.5-V | pasi fa'amatalaga |
| 9 | FSM_D15 | F14 | 2.5-V | pasi fa'amatalaga |
| 85 | SRAM_ADSCN | E6 | 2.5-V | Fa'atonu tulaga o le tuatusi |
| 84 | SRAM_ADSPN | J10 | 2.5-V | Fa'asinomaga tulaga processor |
| 83 | SRAM_ADVN | G6 | 2.5-V | tuatusi aoga |
| 93 | SRAM_BWAN | A3 | 2.5-V | Byte tusitusi filifili |
| 94 | SRAM_BWBN | A2 | 2.5-V | Byte tusitusi filifili |
| 97 | SRAM_CE2 | — | 2.5-V | Chip mafai 2 |
| 92 | SRAM_CE3N | — | 2.5-V | Chip mafai 3 |
| 98 | SRAM_CEN | D7 | 2.5-V | Chip mafai 1 |
| 89 | SRAM_CLK | K10 | 2.5-V | Uati |
| 88 | SRAM_GWN | — | 2.5-V | Fa'aola le tusitusi fa'avaomalo |
| 31 | SRAM_MODE | — | 2.5-V | Filifiliga fa'asologa o le pa |
| 64 | SRAM_ZZ | — | 2.5-V | Faiga moe malosi |
moli
E lagolagoina e le komiti atina'e le 512-Mb CFI-compatible synchronous flash device mo le teuina o le FPGA faʻamaumauga faʻamaumauga, faʻamatalaga o le laupapa, faʻamatalaga o suʻega suʻega, ma avanoa faʻaoga code. O lenei masini o se vaega o le pasi FSM fefaʻasoaaʻi e fesoʻotaʻi i le flash memory, SSRAM, ma MAX V CPLD 5M2210 System Controller. Ole 16-bit data memory interface e mafai ona fa'atumauina fa'agaioiga faitau fa'atopetope e o'o atu ile 52 MHz mo le gaosiga ole 832 Mbps ile masini. O le faʻatinoga o le tusitusi o le 270 μs mo se faʻaupuga e tasi ae o le taimi tape e 800 ms mo le poloka 128 K. O le Siata 2–28 o lo'o lisiina ai galuega mo le pine moli, igoa faailo, ma galuega. O igoa fa'ailo ma ituaiga e fa'atatau ile Afa VE FPGA ile tulaga ole fa'atulagaina ole I/O ma le fa'atonuga.
Laulau 2–28. Fa'atonuga Fa'ailoga Fa'ailoga, Igoa Fa'ailoga Fa'ailoga, ma Galuega (Vaega 1 o le 3)
| Komiti Fa'atonu Fa'asinoga (U10) | Fuafuaga Fa'ailoga Igoa | Afa VE FPGA Numera Pin | I/O Tulaga | Fa'amatalaga |
| F6 | FLASH_ADVN | H12 | 2.5-V | tuatusi aoga |
| B4 | FLASH_CEN | H14 | 2.5-V | Chip mafai |
Laulau 2–28. Fa'atonuga Fa'ailoga Fa'ailoga, Igoa Fa'ailoga Fa'ailoga, ma Galuega (Vaega 2 o le 3)
| Komiti Fa'atonu Fa'asinoga (U10) | Fuafuaga Fa'ailoga Igoa | Afa VE FPGA Numera Pin | I/O Tulaga | Fa'amatalaga |
| E6 | FLASH_CLK | N12 | 2.5-V | Uati |
| F8 | FLASH_OEN | L11 | 2.5-V | Fa'atosina mafai |
| F7 | FLASH_RDYBSYN | J12 | 2.5-V | Sauni |
| D4 | FLASH_RESETN | K11 | 2.5-V | Toe setiina |
| G8 | FLASH_WEN | P12 | 2.5-V | Tusi le mafai |
| C6 | FLASH_WPN | — | 2.5-V | Tusi puipuia |
| A1 | FSM_A1 | B11 | 2.5-V | Tulaga pasi |
| B1 | FSM_A2 | A11 | 2.5-V | Tulaga pasi |
| C1 | FSM_A3 | D9 | 2.5-V | Tulaga pasi |
| D1 | FSM_A4 | C10 | 2.5-V | Tulaga pasi |
| D2 | FSM_A5 | A10 | 2.5-V | Tulaga pasi |
| A2 | FSM_A6 | A9 | 2.5-V | Tulaga pasi |
| C2 | FSM_A7 | C9 | 2.5-V | Tulaga pasi |
| A3 | FSM_A8 | B8 | 2.5-V | Tulaga pasi |
| B3 | FSM_A9 | B7 | 2.5-V | Tulaga pasi |
| C3 | FSM_A10 | A8 | 2.5-V | Tulaga pasi |
| D3 | FSM_A11 | B6 | 2.5-V | Tulaga pasi |
| C4 | FSM_A12 | A6 | 2.5-V | Tulaga pasi |
| A5 | FSM_A13 | C7 | 2.5-V | Tulaga pasi |
| B5 | FSM_A14 | C6 | 2.5-V | Tulaga pasi |
| C5 | FSM_A15 | F13 | 2.5-V | Tulaga pasi |
| D7 | FSM_A16 | E13 | 2.5-V | Tulaga pasi |
| D8 | FSM_A17 | A5 | 2.5-V | Tulaga pasi |
| A7 | FSM_A18 | A4 | 2.5-V | Tulaga pasi |
| B7 | FSM_A19 | J7 | 2.5-V | Tulaga pasi |
| C7 | FSM_A20 | H7 | 2.5-V | Tulaga pasi |
| C8 | FSM_A21 | J9 | 2.5-V | Tulaga pasi |
| A8 | FSM_A22 | H9 | 2.5-V | Tulaga pasi |
| G1 | FSM_A23 | G9 | 2.5-V | Tulaga pasi |
| H8 | FSM_A24 | F8 | 2.5-V | Tulaga pasi |
| B6 | FSM_A25 | E8 | 2.5-V | Tulaga pasi |
| B8 | FSM_A26 | D8 | 2.5-V | Tulaga pasi |
| F2 | FSM_D0 | F16 | 2.5-V | pasi fa'amatalaga |
| E2 | FSM_D1 | E16 | 2.5-V | pasi fa'amatalaga |
| G3 | FSM_D2 | M9 | 2.5-V | pasi fa'amatalaga |
| E4 | FSM_D3 | M8 | 2.5-V | pasi fa'amatalaga |
| E5 | FSM_D4 | F15 | 2.5-V | pasi fa'amatalaga |
| G5 | FSM_D5 | E15 | 2.5-V | pasi fa'amatalaga |
| G6 | FSM_D6 | E12 | 2.5-V | pasi fa'amatalaga |
Laulau 2–28. Fa'atonuga Fa'ailoga Fa'ailoga, Igoa Fa'ailoga Fa'ailoga, ma Galuega (Vaega 3 o le 3)
| Komiti Fa'atonu Fa'asinoga (U10) | Fuafuaga Fa'ailoga Igoa | Afa VE FPGA Numera Pin | I/O Tulaga | Fa'amatalaga |
| H7 | FSM_D7 | D13 | 2.5-V | pasi fa'amatalaga |
| E1 | FSM_D8 | J15 | 2.5-V | pasi fa'amatalaga |
| E3 | FSM_D9 | H15 | 2.5-V | pasi fa'amatalaga |
| F3 | FSM_D10 | E11 | 2.5-V | pasi fa'amatalaga |
| F4 | FSM_D11 | D10 | 2.5-V | pasi fa'amatalaga |
| F5 | FSM_D12 | L10 | 2.5-V | pasi fa'amatalaga |
| H5 | FSM_D13 | L9 | 2.5-V | pasi fa'amatalaga |
| G7 | FSM_D14 | G14 | 2.5-V | pasi fa'amatalaga |
| E7 | FSM_D15 | F14 | 2.5-V | pasi fa'amatalaga |
Paoa sapalai
E mafai ona e fa'aola le laupapa atina'e mai se fa'aoga eletise DC fa'akomepiuta. O le fa'aoga voltage tatau ona iai ile va ole 14 V i le 20 V, ole taimi nei ole 4.3 A, ma le maualuga ole wat.tage o le 65 W. O le DC voltagOna la'a lea i lalo i laina eletise eseese o lo'o fa'aogaina e vaega o le laupapa ma fa'apipi'i i feso'ota'iga HSMC. O se fa'aliliuga analog-i-numera (ADC) i luga o le laupapa e fuaina ai le taimi nei mo le tele o ala laupapa fa'apitoa.
Malosiaga Faasoasoaina Polokalama
Ata 2–9 o lo'o fa'aalia ai le faiga o le tufatufaina atu o le eletise i luga o le laupapa atina'e. O le le atoatoa ma le fa'asoa o lo'o fa'aalia i le au o lo'o fa'aalia, o lo'o fa'atumauina le maualuga maualuga.
Ata 2–9. Faiga Fa'asoa Malosi
Fuaina o le Malosi
E valu laina eletise o loʻo iai i luga o le vaʻa o loʻo i ai le malosi faʻaogaina o loʻo faʻaogaina ai le 24-bit differential ADC masini. Sa'o lagona tetee vaevae masini ADC ma alavai mai le vaalele sapalai muamua mo le ADC e fua ai le taimi nei. E feso'ota'i se pasi SPI nei masini ADC i le MAX V CPLD 5M2210 System Controller.
O le Ata 2–10 o lo'o fa'aalia ai le poloka poloka mo le si'osi'omaga e fua ai le malosi.
Ata 2–10. Li'o Fuaina o le Malosi
Siata 2–29 o lo'o lisiina ai ala fa'atatau. O le koluma o le igoa faailoilo o lo'o fa'amaoti mai ai le igoa o le nofoa afi o lo'o fuaina a'o le koluma pine o le masini o lo'o fa'amaoti mai ai masini e fa'apipi'i i le nofoa afi.
Laulau 2–29. Ala e fua ai le malosi
| Auala | Fuafuaga Fa'ailoga Igoa | Voltage (V) | Meafaigaluega Pin | Fa'amatalaga |
| 1 | VCC | 1.1 | VCC | Malosiaga autu FPGA |
| 2 | VCCAUX | 2.5 | VCC_AUX | Ausilali |
| 3 | VCCA_FPLL | 2.5 | VCCA_FPLL | PLL analog mana |
| VCCPD3B4A, | ||||
| VCCPD5A,
VCCPD5B, VCCPD6A, |
I/O muamua aveta'avale faletupe 3B, 4A, 5A, 5B, 6A, 7A, ma le 8A | |||
| 5 | VCCIO_VCCPD_2.5V | 2.5 | VCCPD7A8A | |
| VCCIO3B, | ||||
| VCCIO6A, VCCIO7A, | VCC I/O faletupe 3B, 6A, 7A, ma le 8A | |||
| VCCIO8A | ||||
| 7 | VCCIO_1.2V | 1.2 | VCCIO5A, VCCIO5B, | VCC I/O faletupe 5A ma 5B (LPDDR2) |
| 8 | VCCIO_1.5V | 1.5 | VCCIO_4A | VCC I/O faletupe 4A (DDR3) |
Fa'amatalaga Vaega a le Komiti Fa'atonu
O lenei mataupu o lo'o fa'amatala ai vaega o le komiti fa'atupuina o le Afa VE FPGA, fa'amatalaga o gaosiga, ma fa'amatalaga o le tausisia e le komiti.
Vaega Komiti
O lo'o lisiina i luga ole laulau le vaega fa'asinomaga ma fa'amatalaga o le gaosiga o vaega uma ile laupapa atina'e.
Laulau 3–1. Faʻamatalaga Faʻamatalaga ma Faʻamatalaga Gaosi Mea
| Komiti Fa'atonu Fa'asinomaga | Vaega | Tufuga | Gaosimea Numera Vaega | Tufuga Webnofoaga |
| U1 | FPGA, Afa VE F896, 149,500
LE, leai se ta'ita'i |
Altera Faalapotopotoga | 5CEFA7F31I7N | www.altera.com |
| U13 | MAX V CPLD 5M2210 Faiga
Pule |
Altera Faalapotopotoga | 5M2210ZF256I5N | www.altera.com |
| U18 | Fa'atonu pito i luga ole USB ole televave | Cypress | CY7C68013A | www.cypress.com |
| D1-D16, D18-D31, | LED lanu meamata | Lumex Inc. | SML-LXT0805GW-TR | www.lumex.com |
| D17 | LED mumu | Lumex Inc. | SML-LXT0805IW-TR | www.lumex.com |
| D35 | LED lanumoana | Lumex Inc. | SML-LX0805USBC-TR | www.lumex.com |
| SW1–SW4 | Fa-tulaga DIP ki | C&K Components/ ITT Alamanuia | TDA04H0SB1 | www.ittcannon.com |
| S1-S8 | Tulei faʻamau | Panasonic | EVQPAC07K | www.panasonic.com |
| S5 | Su'e solo | E-sui | EG2201A | www.e-switch.com |
| X1 | Uati LVDS polokalame 125M faaletonu | Silicon Labs | 570FAB000973DG | www.Salasbs.com |
| X3 | 100 MHz tioata tioata, ±50 ppm,
CMOS, 2.5 V |
Silicon Labs | 510GBA100M000BAGx | www.Salasbs.com |
| X2 | 50 MHz tioata tioata, ±50 ppm,
CMOS, 2.5 V |
Silicon Labs | 510GBA50M0000BAGx | www.Salasbs.com |
| J12 | Fema'i fa'amauina PCB WR-DSUB 9-pine feso'ota'iga | Wurth Electronic | 618009231121 | www.we-online.com |
| U21 | USB-i-UART alalaupapa | Silicon Labs | CP2104 | www.Salasbs.com |
| J14 | 2×7 pine LCD socket strip | Samtec | TSM-107-07-GD | www.samtec.com |
| 2x16 amio LCD, 5x8 mata'itusi | Lumex Inc. | LCM-S01602DSR/C | www.lumex.com | |
| U14, U15 | Ethernet PHY BASE-T masini | Marvell Semiconductor | 88E1111-B2- CAA1C000 | www.marvell.com |
| J8, J9 | RJ-45 so'oga, 10/100/1000 Mbps | Wurth Electronic | 7499111001A | www.we-online.com |
| J7 | HSMC, fa'asologa masani o le QSH-DP aiga saosaoa socket. | Samtec | ASP-122953-01 | www.samtec.com |
| U20 | RS-232 lua transceiver | Tekinolosi Linear | LTC2803-1 | www.linear.com |
Laulau 3–1. Faʻamatalaga Faʻamatalaga ma Faʻamatalaga Gaosi Mea
| Komiti Fa'atonu Fa'asinomaga | Vaega | Tufuga | Gaosimea Numera Vaega | Tufuga Webnofoaga |
| U12 | 64-Kb EEPROM | Microchip | 24AA64 | www.microchip.com |
| J15, J16 | 2 x 8 fa'aulu fa'aliga | Samtec | TSM-108-01-L-DV | www.samtec.com |
| U7, U8 | 16M × 16 × 8, 256-MB DDR3 SDRAM | Micron | MT41J128M16 | www.micron.com |
| U9 | 16M × 32 × 8, 512-MB LPDDR2 SDRAM | Micron | MT42L128M32 | www.micron.com |
| U11 | 1024K × 18 bit 18-Mb synchronous SRAM | Integrated Silicon Solution, Inc. | IS61VPS102418A- 250TQL | www.issi.com |
| U10 | 512-Mb moli fa'atasi | Numonyx | PC28F512P30BF | www.numonyx.com |
| U35 | 16-auala eseese 24-bit ADC | Tekinolosi Linear | LTC2418CGN#PBF | www.linear.com |
Faʻamatalaga o le tausisia o Saina-RoHS
Lisi 3–2 o lo'o lisi ai mea mata'utia o lo'o i totonu o le pusa.
Laulau 3–2. Lisi o Igoa o Vailaau Mata'utia ma Fa'amatalaga (1), (2)
|
Vaega Igoa |
Ta'ita'i (Pb) | Cadmium (Cd) | Faʻamalosi Chromium (Cr6 +) | Mercury (Hg) | Polybrominated biphenyls (PBB) | Polybrominated diphenyl Eteru (PBDE) |
| Komiti Fa'atino o Atina'e Afa VE | X* | 0 | 0 | 0 | 0 | 0 |
| 15 V eletise sapalai | 0 | 0 | 0 | 0 | 0 | 0 |
| Ituaiga AB USB uaea | 0 | 0 | 0 | 0 | 0 | 0 |
| Fa'aoga ta'iala | 0 | 0 | 0 | 0 | 0 | 0 |
Fa'amatalaga ile Laulau 3–2:
- 0 o loʻo faʻaalia ai o le faʻaogaina o mea matautia i mea tutusa uma i totonu o vaega o loʻo i lalo ole tulaga talafeagai ole SJ/T11363-2006.
- X * o loʻo faʻaalia ai o le faʻaogaina o mea mataʻutia o le itiiti ifo ma le tasi o mea tutusa uma i totonu o vaega o loʻo i luga aʻe o le faʻailoga talafeagai o le SJ / T11363-2006 tulaga, ae e tuusaunoaina e le EU RoHS.
CE EMI Fa'atonu Fa'aeteete
O lenei pusa atina'e o lo'o tu'uina atu e tusa ai ma tulaga fa'atatau e fa'atulafonoina e le Fa'atonu 2004/108/EC. Ona o le natura o masini faʻapolokalame faʻaogaina, e mafai e le tagata faʻaoga ona suia le pusa i se auala e faʻatupu ai le faʻalavelave electromagnetic (EMI) e sili atu i tapulaʻa ua faʻatuina mo lenei meafaigaluega. So'o se EMI na mafua ona o suiga i mea na tu'uina atu o le matafaioi a le tagata fa'aoga.
Fa'amatalaga Faaopoopo
O lenei mataupu o loʻo tuʻuina atu ai faʻamatalaga faaopoopo e uiga i le pepa ma Altera.
Tala'aga Toe Iloilo a le Komiti Fa'atonu
O le siata o lo'o i lalo o lo'o lisiina ai fa'amatalaga o fa'asalalauga uma a le Komiti Fa'atino o Atina'e VE VE FPGA.
| Fa'asa'oloto Aso | Fa'aliliuga | Fa'amatalaga |
| Mati 2013 | Gaosiga silikoni | ■ Toe iloiloga fou a le komiti. Numera vaega ole masini fou—5CEFA7F31I7N.
■ Ua pasia e le Komiti le su'ega o le tausisia o le CE. |
| Novema 2012 | Inisinia silikoni | Fa'asalalauga muamua. |
Talafaasolopito Toe Iloiloga o Pepa
O le laulau o lo'o i lalo o lo'o lisiina ai le tala fa'asolopito o le toe iloiloga mo lenei pepa.
| Aso | Fa'aliliuga | Suiga |
| Aokuso 2017 | 1.4 | Fa'asa'o le nofoaga laupapa mo le Uati Output SMA Connector i “Ua umaview o le Avanoa a le Afa VE FPGA Development Board” i le itulau 2–2. |
| Ianuari 2017 | 1.3 | Fa'asa'o le numera pine ENETA_RX_DV i totonu Laulau 2–20 i le itulau 2–25. |
|
Setema 2015 |
1.2 |
■ Faaopoopo le sootaga i Altera Design Faleoloa in “MAX V CPLD 5M2210 System Controller” i luga itulau 2–5.
■ Fa'asa'o le igoa o masini i totonu Ata 2–5 i le itulau 2–15. |
| Mati 2013 | 1.1 | ■ Toe fa'aleleia le numera vaega ole masini FPGA mo le fa'asa'olotoina o le silikoni.
■ Faaopoopoina se vaega e uiga i “CE EMI Conformity Lapataiga” i le itulau 3–2. |
| Novema 2012 | 1.0 | Fa'asalalauga muamua. |
Fonotaga Tusitusi
O le siata o lo'o i lalo o lo'o fa'aalia ai tulafono fa'akomipiuta o lo'o fa'aogaina e lenei pepa.
| Vaaia Fa'ailoa | Uiga |
| Ituaiga Malosia ma Uluai Ulutala Tusi | Fa'ailoa igoa o le fa'atonuga, fa'aigoa o le pusa fa'atalanoaga, filifiliga pusa fa'amatalaga, ma isi fa'ailoga GUI. Mo example, Save As pusa talanoa. Mo elemene GUI, mataitusi tetele e fetaui ma le GUI. |
|
lototoa ituaiga |
Fa'ailoa igoa fa'atonu, igoa o galuega, igoa ta'avale tisiki, file igoa, file fa'aopoopoga igoa, igoa fa'aoga polokalame, ma fa'ailoga GUI. Mo example, \qdesigns tusi tusi, D: ave taavale, ma chiptrip.gdf file. |
| Ituaiga Fa'asisi ma Mataitusi Mataitusi Ulua'i | Fa'ailoa igoa o pepa. Mo example, Stratix IV Fuafuaga Taiala. |
Komiti Fa'atino o Atina'e o le Afa V E FPGA
Tusi Taiala
Aukuso 2017 Altera Corporation
Pepa / Punaoa
 |
ALTERA Afa VE FPGA Komiti Fa'atino [pdf] Tusi Taiala Afa VE FPGA Komiti Atina'e, Afa, VE FPGA Komiti Atina'e, Komiti Fa'atino FPGA, Komiti Fa'atino, Komiti Fa'atonu |
